Datasheet

RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: T
A = -40 to +105°C)
Page 142 of 194R01DS0131EJ0310 Rev.3.10
Nov 15, 2013
3.4 AC Characteristics
(TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Instruction cycle (minimum
instruction execution time)
TCY Main
system
clock (f
MAIN)
operation
HS (high-speed
main) mode
2.7 V ≤ V DD ≤ 5.5 V 0.03125 1 μ s
2.4 V ≤ V DD < 2.7 V 0.0625 1 μ s
Subsystem clock (fSUB)
operation
2.4 V ≤ V DD ≤ 5.5 V 28.5 30.5 31.3 μ s
In the self
programming
mode
HS (high-speed
main) mode
2.7 V ≤ V DD ≤ 5.5 V 0.03125 1 μ s
2.4 V ≤ V DD < 2.7 V 0.0625 1 μ s
External system clock frequency fEX 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz
2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz
fEXS 32 35 kHz
External system clock input high-
level width, low-level width
tEXH, tEXL 2.7 V ≤ VDD ≤ 5.5 V 24 ns
2.4 V ≤ VDD < 2.7 V 30 ns
tEXHS,
t
EXLS
13.7
μ s
TI00 to TI07, TI10 to TI17 input
high-level width, low-level width
tTIH,
t
TIL
1/f
MCK+10 ns
Note
TO00 to TO07, TO10 to TO17
output frequency
fTO
HS (high-speed
main) mode
4.0 V ≤ EV
DD0 ≤ 5.5 V 16 MHz
2.7 V ≤ EVDD0 < 4.0 V 8 MHz
2.4 V ≤ EVDD0 < 2.7 V 4 MHz
PCLBUZ0, PCLBUZ1 output
frequency
fPCL HS (high-speed
main) mode
4.0 V ≤ EVDD0 ≤ 5.5 V 16 MHz
2.7 V ≤ EVDD0 < 4.0 V 8 MHz
2.4 V ≤ EVDD0 < 2.7 V 4 MHz
Interrupt input high-level width,
low-level width
tINTH,
t
INTL
INTP0 2.4 V ≤ V
DD ≤ 5.5 V 1 μ s
INTP1 to INTP11 2.4 V ≤ EVDD0 ≤ 5.5 V 1 μ s
Key interrupt input low-level width tKR KR0 to KR7 2.4 V ≤ EVDD0 ≤ 5.5 V 250 ns
RESET low-level width tRSL 10 μ s
Note The following conditions are required for low voltage interface when E
VDD0 < VDD
2.4V ≤ EVDD0 < 2.7 V : MIN. 125 ns
Remark f
MCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn).
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7))