Datasheet

RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: T
A = -40 to +85°C)
Page 107 of 194R01DS0131EJ0310 Rev.3.10
Nov 15, 2013
(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I
2
C mode) (2/2)
(T
A = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Data setup time
(reception)
t
SU:DAT
4.0 V ≤ EV
DD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V,
C
b = 50 pF, Rb = 2.7 kΩ
1/f
MCK +
135
Note
3
1/f
MCK
+ 190
Note 3
1/fMCK
+ 190
Note 3
kHz
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 50 pF, Rb = 2.7 kΩ
1/f
MCK +
135
Note
3
1/f
MCK
+ 190
Note 3
1/fMCK
+ 190
Note 3
kHz
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V,
C
b = 100 pF, Rb = 2.8 kΩ
1/f
MCK +
190
Note
3
1/f
MCK
+ 190
Note 3
1/fMCK
+ 190
Note 3
kHz
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 100 pF, Rb = 2.7 kΩ
1/f
MCK +
190
Note
3
1/f
MCK
+ 190
Note 3
1/fMCK
+ 190
Note 3
kHz
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
Note 2
,
C
b = 100 pF, Rb = 5.5 kΩ
1/f
MCK +
190
Note
3
1/f
MCK
+ 190
Note 3
1/fMCK
+ 190
Note 3
kHz
Data hold time
(transmission)
t
HD:DAT
4.0 V ≤ EV
DD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V,
C
b = 50 pF, Rb = 2.7 kΩ
0 305 0 305 0 305 ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 50 pF, Rb = 2.7 kΩ
0
305
0
305
0
305
ns
4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V,
C
b = 100 pF, Rb = 2.8 kΩ
0
355
0
355
0
355
ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 100 pF, Rb = 2.7 kΩ
0
355
0
355
0
355
ns
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
Note 2
,
C
b = 100 pF, Rb = 5.5 kΩ
0
405
0
405
0
405
ns
Notes 1. The value must also be equal to or less than f
MCK/4.
2. Use it with EV
DD0 ≥ Vb.
3. Set the f
MCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution Select the TTL input buffer and the N-ch open drain output (V
DD tolerance (When 20- to 52-pin
products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SDAr pin and the N-ch
open drain output (V
DD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-
pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output
mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)