Datasheet

RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: T
A = -40 to +85°C)
Page 103 of 194R01DS0131EJ0310 Rev.3.10
Nov 15, 2013
(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock
input)
(TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter Symbol Conditions HS (high-
speed main)
Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp high-/low-level
width
tKH2,
t
KL2
4.0 V ≤ EV
DD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V
t KCY2/2
− 12
t KCY2/2
− 50
t KCY2/2
− 50
ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V
t KCY2/2
− 18
t KCY2/2
− 50
t KCY2/2
− 50
ns
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
Note 2
t KCY2/2
− 50
t KCY2/2
− 50
t KCY2/2
− 50
ns
SIp setup time
(to SCKp↑)
Note 3
t
SIK2 4.0 V ≤ EVDD0 ≤ 5.5 V,
2.7 V ≤ V
b ≤ 4.0 V
1/f
MCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
ns
2.7 V ≤ EVDD0 < 4.0 V,
2.3 V ≤ V
b ≤ 2.7 V
1/f
MCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
ns
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
Note 2
1/f
MCK
+ 30
1/fMCK
+ 30
1/fMCK
+ 30
ns
SIp hold time
(from SCKp↑)
Note 4
t
KSI2 1/fMCK +
31
1/fMCK
+ 31
1/fMCK
+ 31
ns
Delay time from
SCKp↓ to SOp output
Note 5
t
KSO2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0
V,
C
b = 30 pF, Rb = 1.4 kΩ
2/f
MCK
+ 120
2/fMCK
+ 573
2/fMCK
+ 573
ns
2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7
V,
C
b = 30 pF, Rb = 2.7 kΩ
2/f
MCK
+ 214
2/fMCK
+ 573
2/fMCK
+ 573
ns
1.8 V ≤ EVDD0 < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V
Note 2
,
C
b = 30 pF, Rb = 5.5 kΩ
2/f
MCK
+ 573
2/fMCK
+ 573
2/fMCK
+ 573
ns
Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
2. Use it with EV
DD0 ≥ Vb.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V
DD tolerance (When
20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For
V
IH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)