Datasheet RL78/G13 R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 RENESAS MCU True Low Power Platform (as low as 66 µA/MHz, and 0.57 µA for RTC + LVD), 1.6 V to 5.5 V operation, 16 to 512 Kbyte Flash, 41 DMIPS at 32 MHz, for General Purpose Applications 1. OUTLINE 1.1 Features Ultra-Low Power Technology • 1.6 V to 5.5 V operation from a single supply • Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31 µA • Halt (RTC + LVD): 0.57 µA • Snooze: 0.70 mA (UART), 1.
RL78/G13 1.
RL78/G13 1. OUTLINE 1.2 List of Part Numbers Figure 1-1. Part Number, Memory Size, and Package of RL78/G13 Part No. R 5 F 1 0 0 L E A x x x F B #V0 Packaging specification #U0 #V0 #W0 #X0 : Tray (HWQFN,VFBGA,WFLGA) : Tray (LFQFP,LQFP,LSSOP) : Embossed Tape (HWQFN,VFBGA,WFLGA) : Embossed Tape (LFQFP, LQFP, LSSOP) Package type: SP: LSSOP, 0.65 mm pitch FP : LFQFP, 0.80 mm pitch FA : LFQFP, 0.65 mm pitch FB : LFQFP, 0.50 mm pitch NA : HWQFN, 0.50 mm pitch LA : WFLGA, 0.50 mm pitch Note 1 BG : VFBGA, 0.
RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers (1/12) Pin Package count Data Fields of flash Application Ordering Part Number Note 20 pins 20-pin plastic LSSOP Mounted A R5F1006AASP#V0, R5F1006CASP#V0, R5F1006DASP#V0, (7.62 mm (300), 0.
RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers (2/12) Pin count Package Data flash Fields of Application Ordering Part Number Note 25 pins 25-pin plastic WFLGA (3 × 3 mm, Mounted A Not mounted A Mounted A 0.5 mm pitch) 30 pins 30-pin plastic LSSOP (7.62 mm (300), 0.65 mm pitch) D G Not mounted A D 32 pins 32-pin plastic HWQFN (5 × 5 mm, Mounted A 0.
RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers (3/12) Pin Package count Data Fields of flash Application Ordering Part Number Note 36 pins 36-pin plastic WFLGA (4 × 4 mm, 0.
RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers (4/12) Pin Package Data flash count Ordering Part Number Fields of Application Note 44 pins 44-pin plastic LQFP Mounted A R5F100FAAFP#V0, R5F100FCAFP#V0, R5F100FDAFP#V0, (10 × 10 mm, 0.
RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers (5/12) Pin count Package Data flash Ordering Part Number Fields of Application Note 48 pins 48-pin plastic LFQFP Mounted A R5F100GAAFB#V0, R5F100GCAFB#V0, R5F100GDAFB#V0, (7 × 7 mm, 0.
RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers (6/12) Pin count Package Data flash Ordering Part Number Fields of Application Note 48 pins 48-pin plastic Mounted A R5F100GAANA#U0, R5F100GCANA#U0, R5F100GDANA#U0, HWQFN (7 × 7 R5F100GEANA#U0, R5F100GFANA#U0, R5F100GGANA#U0, mm, 0.
RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers (7/12) Pin Package Data flash Ordering Part Number Fields of count Application Note 52 pins 52-pin plastic LQFP Mounted A R5F100JCAFA#V0, R5F100JDAFA#V0, R5F100JEAFA#V0, (10 × 10 mm, 0.
RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers (8/12) Pin count Package Data flash Ordering Part Number Fields of Application Note 64 pins 64-pin plastic LQFP Mounted A R5F100LCAFA#V0, R5F100LDAFA#V0, R5F100LEAFA#V0, (12 × 12 mm, 0.
RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers (9/12) Pin count Package Data flash Ordering Part Number Fields of Application Note 64 pins 64-pin plastic LFQFP Mounted A R5F100LCAFB#V0, R5F100LDAFB#V0, R5F100LEAFB#V0, (10 × 10 mm, 0.
RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers (10/12) Pin count Package Data flash Ordering Part Number Fields of Application Note 80 pins 80-pin plastic Mounted A R5F100MFAFA#V0, R5F100MGAFA#V0, R5F100MHAFA#V0, LQFP R5F100MJAFA#V0, R5F100MKAFA#V0, R5F100MLAFA#V0 (14 × 14 mm, 0.
RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers (11/12) Pin count Package Data flash Ordering Part Number Fields of Application Note 100 pins 100-pin plastic Mounted A R5F100PFAFB#V0, R5F100PGAFB#V0, R5F100PHAFB#V0, LFQFP (14 × 14 R5F100PJAFB#V0, R5F100PKAFB#V0, R5F100PLAFB#V0 mm, 0.
RL78/G13 1. OUTLINE Table 1-1. List of Ordering Part Numbers (12/12) Pin count Package Data flash Fields of Ordering Part Number Application Note 128 pins 128-pin plastic LFQFP Mounted A R5F100SHAFB#V0, R5F100SJAFB#V0, (14 × 20 mm, 0.
RL78/G13 1. OUTLINE 1.3 Pin Configuration (Top View) 1.3.1 20-pin products • 20-pin plastic LSSOP (7.62 mm (300), 0.
RL78/G13 1. OUTLINE 1.3.2 24-pin products P22/ANI2 P147/ANI18 P10/SCK00/SCL00 P11/SI00/RxD0/TOOLRxD/SDA00 P12/SO00/TxD0/TOOLTxD P16/TI01/TO01/INTP5 • 24-pin plastic HWQFN (4 × 4 mm, 0.
RL78/G13 1. OUTLINE 1.3.3 25-pin products • 25-pin plastic WFLGA (3 × 3 mm, 0.
RL78/G13 1. OUTLINE 1.3.4 30-pin products • 30-pin plastic LSSOP (7.62 mm (300), 0.
RL78/G13 1. OUTLINE 1.3.5 32-pin products P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) • 32-pin plastic HWQFN (5 × 5 mm, 0.
RL78/G13 1. OUTLINE 1.3.6 36-pin products • 36-pin plastic WFLGA (4 × 4 mm, 0.
RL78/G13 1. OUTLINE 1.3.7 40-pin products P147/ANI18 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) P51/INTP2/SO11 • 40-pin plastic HWQFN (6 × 6 mm, 0.
RL78/G13 1. OUTLINE 1.3.8 44-pin products P147/ANI18 P146 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) P51/INTP2/SO11 • 44-pin plastic LQFP (10 × 10 mm, 0.
RL78/G13 1. OUTLINE 1.3.9 48-pin products P140/PCLBUZ0/INTP6 P00/TI00/TxD1 P01/TO00/RxD1 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 • 48-pin plastic LFQFP (7 × 7 mm, 0.
RL78/G13 1. OUTLINE P140/PCLBUZ0/INTP6 P00/TI00/TxD1 P01/TO00/RxD1 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 • 48-pin plastic HWQFN (7 × 7 mm, 0.
RL78/G13 1. OUTLINE 1.3.10 52-pin products P30/INTP3/RTC1HZ/SCK11/SCL11 P50/INTP1/SI11/SDA11 P51/INTP2/SO11 P17/TI02/TO02/(TXD0) P16/TI01/TO01/INTP5/(RXD0) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P10/SCK00/SCL00/(TI07)/(TO07) P146 P147/ANI18 • 52-pin plastic LQFP (10 × 10 mm, 0.
RL78/G13 1. OUTLINE 1.3.11 64-pin products • 64-pin plastic LQFP (12 × 12 mm, 0.
RL78/G13 1. OUTLINE • 64-pin plastic VFBGA (4 × 4 mm, 0.4 mm pitch) Top View Bottom View 8 7 6 5 4 3 2 1 A B C D E F G H H G F E D C B A Index mark Pin No. Name Pin No. Name Pin No. Name Pin No.
RL78/G13 1. OUTLINE 1.3.12 80-pin products • 80-pin plastic LQFP (14 × 14 mm, 0.
RL78/G13 1. OUTLINE 1.3.
RL78/G13 1. OUTLINE P140/PCLBUZ0/INTP6 P141/PCLBUZ1/INTP7 P142/SCK30/SCL30 P143/SI30/RxD3/SDA30 P144/SO30/TxD3 P145/TI07/TO07 P00/TI00 P01/TO00 P02/ANI17/SO10/TxD1 P03/ANI16/SI10/RxD1/SDA10 P04/SCK10/SCL10 P102/TI06/TO06 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 P150/ANI8 P151/ANI9 P152/ANI10 P153/ANI11 P154/ANI12 P155/ANI13 P156/ANI14 P100/ANI20 P147/ANI18 • 100-pin plastic LQFP (14 × 20 mm, 0.
RL78/G13 1. OUTLINE 1.3.
RL78/G13 1. OUTLINE 1.
RL78/G13 1. OUTLINE 1.5 Block Diagram 1.5.
RL78/G13 1. OUTLINE 1.5.
RL78/G13 1. OUTLINE 1.5.
RL78/G13 1. OUTLINE 1.5.
RL78/G13 1. OUTLINE 1.5.
RL78/G13 1. OUTLINE 1.5.
RL78/G13 1. OUTLINE 1.5.
RL78/G13 1. OUTLINE 1.5.
RL78/G13 1. OUTLINE 1.5.
RL78/G13 1. OUTLINE 1.5.
RL78/G13 1. OUTLINE 1.5.
RL78/G13 1. OUTLINE 1.5.
RL78/G13 1. OUTLINE 1.5.
RL78/G13 1. OUTLINE 1.5.
RL78/G13 1. OUTLINE 1.6 Outline of Functions [20-pin, 24-pin, 25-pin, 30-pin, 32-pin, 36-pin products] Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H.
RL78/G13 1. OUTLINE (2/2) Item 20-pin 24-pin R5F101Cx R5F100Cx 2 36-pin R5F101Bx 1 32-pin R5F100Bx R5F101Ax R5F100Ax 1 30-pin R5F1018x R5F1008x R5F1017x R5F1007x R5F1016x R5F1006x − Clock output/buzzer output 25-pin 2 2 • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.
RL78/G13 1. OUTLINE [40-pin, 44-pin, 48-pin, 52-pin, 64-pin products] Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H.
RL78/G13 1. OUTLINE (2/2) Item 40-pin 64-pin R5F101Lx R5F100Lx R5F101Jx 2 R5F100Jx 2 52-pin R5F101Gx R5F100Gx 2 48-pin R5F101Fx R5F100Fx R5F101Ex R5F100Ex Clock output/buzzer output 44-pin 2 2 • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) • 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.
RL78/G13 1. OUTLINE [80-pin, 100-pin, 128-pin products] Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H.
RL78/G13 1. OUTLINE (2/2) Item 80-pin R5F100Mx Clock output/buzzer output 100-pin R5F101Mx R5F100Px 2 R5F101Px 128-pin R5F100Sx 2 R5F101Sx 2 • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) • 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) This chapter describes the electrical specifications for the products "A: Consumer applications (TA = -40 to +85°C)" and "D: Industrial applications (TA = -40 to +85°C)". Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25°C) (1/2) Parameter Supply voltage Symbols Conditions Ratings Unit VDD −0.5 to +6.5 V EVDD0, EVDD1 EVDD0 = EVDD1 −0.5 to +6.5 V EVSS0, EVSS1 −0.5 to +0.3 V −0.3 to +2.8 and −0.3 to VDD +0.3Note 1 V −0.3 to EVDD0 +0.
RL78/G13 2.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.2 Oscillator Characteristics 2.2.1 X1, XT1 oscillator characteristics (TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter X1 clock oscillation frequency (fX)Note XT1 clock oscillation frequency (fX)Note Resonator Ceramic resonator/ crystal resonator Conditions MIN. TYP. MAX. Unit 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz 2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz 1.8 V ≤ VDD < 2.4 V 1.0 8.0 MHz 1.6 V ≤ VDD < 1.8 V 1.0 4.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.3 DC Characteristics 2.3.1 Pin characteristics (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/5) Items Symbol Output current, highNote 1 IOH1 MAX. Unit 1.6 V ≤ EVDD0 ≤ 5.5 V Per pin for P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 Conditions −10.0 mA 4.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/5) Items Symbol Output current, lowNote 1 IOL1 Conditions MIN. TYP. Per pin for P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 20.0 mA Per pin for P60 to P63 15.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/5) Items Input voltage, high Input voltage, low Symbol Conditions MIN.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (4/5) Items Symbol Output voltage, high Output voltage, low VOH1 Conditions P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 MIN. TYP. MAX. Unit 4.0 V ≤ EVDD0 ≤ 5.5 V, EVDD0 − IOH1 = −10.0 mA 1.5 V 4.0 V ≤ EVDD0 ≤ 5.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (5/5) Items Input leakage current, high Symbol Conditions MIN. TYP.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.3.2 Supply current characteristics (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (1/2) Parameter Supply current Note 1 Symbol IDD1 Conditions fIH = 32 MHz Operating HS (highmode speed main) mode Note 5 Note 3 MIN. TYP. MAX. Unit Basic operation VDD = 5.0 V 2.1 mA VDD = 3.0 V 2.1 mA Normal operation VDD = 5.0 V 4.6 7.0 mA VDD = 3.0 V 4.6 7.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (2/2) Parameter Symbol Supply current IDD2 Note 2 Conditions HALT mode Note 1 HS (highspeed main) mode Note 7 LS (lowspeed main) mode Note 7 LV (lowvoltage main) mode MIN. TYP. MAX. Unit VDD = 5.0 V 0.54 1.63 mA VDD = 3.0 V 0.54 1.63 mA VDD = 5.0 V 0.44 1.28 mA VDD = 3.0 V 0.44 1.28 mA VDD = 5.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol IDD1 Supply currentNote 1 Conditions Operating mode HS (highspeed main) mode Note 5 MIN. fIH = 32 MHz Note 3 Basic VDD = 5.0 V operation VDD = 3.0 V Normal VDD = 5.0 V operation VDD = 3.0 V TYP. MAX. 2.3 Unit mA 2.3 mA 5.2 8.5 mA 5.2 8.5 mA 4.1 6.6 mA 4.1 6.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Parameter Symbol Supply current IDD2 Note 2 Conditions HALT mode Note 1 HS (highspeed main) mode Note 7 fIH = 32 MHz Note 4 fIH = 24 MHz Note 4 fIH = 16 MHz Note 4 LS (lowspeed main) mode Note 7 fIH = 8 MHz Note 4 LV (lowvoltage main) mode fIH = 4 MHz Note 4 MIN. VDD = 5.0 V TYP. MAX.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current .
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (3) 128-pin products, and flash ROM: 384 to 512 KB of 44- to 100-pin products (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol IDD1 Supply current Note 1 Conditions fIH = 32 MHz Note 3 Operating HS (highmode speed main) mode Note 5 fIH = 24 MHz fIH = 16 MHz fIH = 8 MHz LS (lowspeed main) mode Note 5 LV (lowvoltage main) mode Note 3 Note 3 Note 3 fIH = 4 MHz Note 3 MIN. TYP.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (3) 128-pin products, and flash ROM: 384 to 512 KB of 44- to 100-pin products (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Parameter Symbol Supply current IDD2 Note 2 Conditions HALT mode Note 1 HS (highspeed main) mode Note 7 fIH = 32 MHz Note 4 fIH = 24 MHz Note 4 fIH = 16 MHz Note 4 LS (lowspeed main) mode Note 7 fIH = 8 MHz Note 4 LV (lowvoltage main) mode fIH = 4 MHz Note 4 TYP.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current .
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (4) Peripheral Functions (Common to all products) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit IFILNote 1 0.20 μA RTC operating current IRTC Notes 1, 2, 3 0.02 μA 12-bit interval IIT Notes 1, 2, 4 0.02 μA 0.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. 7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation. 8. Current flowing only during data flash rewrite. 9.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.4 AC Characteristics (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Instruction cycle (minimum instruction execution time) Symbol TCY Conditions Main HS (highsystem speed main) clock (fMAIN) mode operation MIN. MAX. Unit 2.7 V ≤ VDD ≤ 5.5 V 0.03125 1 μs 2.4 V ≤ VDD < 2.7 V 0.0625 1 μs 0.125 1 μs 1.6 V ≤ VDD ≤ 5.5 V 0.25 1 μs 1.8 V ≤ VDD ≤ 5.5 V 28.5 31.3 μs 2.7 V ≤ VDD ≤ 5.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Note The following conditions are required for low voltage interface when EVDD0 < VDD 1.8 V ≤ EVDD0 < 2.7 V : MIN. 125 ns 1.6 V ≤ EVDD0 < 1.8 V : MIN. 250 ns Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn).
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) TCY vs VDD (LS (low-speed main) mode) Cycle time TCY [µs] 10 1.0 When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.125 0.1 0.01 0 1.0 2.0 1.8 3.0 4.0 5.0 5.5 6.0 Supply voltage VDD [V] TCY vs VDD (LV (low-voltage main) mode) Cycle time TCY [µs] 10 1.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) AC Timing Test Points VIH/VOH VIL/VOL VIH/VOH Test points VIL/VOL External System Clock Timing 1/fEX/ 1/fEXS tEXL/ tEXLS tEXH/ tEXHS EXCLK/EXCLKS TI/TO Timing tTIH tTIL TI00 to TI07, TI10 to TI17 1/fTO TO00 to TO07, TO10 to TO17 Interrupt Request Input Timing tINTH tINTL INTP0 to INTP11 Key Interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET R01DS0131EJ0310 Rev.3.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.5 Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL 2.5.1 Serial array unit (1) During communication at same potential (UART mode) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. Transfer rate Note 1 MAX. 2.4 V≤ EVDD0 ≤ 5.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) UART mode connection diagram (during communication at same potential) Rx TxDq User device RL78 microcontroller RxDq Tx UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remarks 1. 2.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = −40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode MIN.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 1, 4, 5, 8, 14) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) (4) During communication at same potential (CSI mode) (slave mode, SCKp...
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (2/2) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SIp setup time (to SCKp↑) Note tSIK2 1 tKSI2 Note 2 tKSO2 MAX. MIN. MAX. 1/fMCK+2 0 1/fMCK+30 1/fMCK+3 0 ns 1.8 V ≤ EVDD0 ≤ 5.5 V 1/fMCK+3 0 1/fMCK+30 1/fMCK+3 0 ns 1.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) CSI mode connection diagram (during communication at same potential) SCK SCKp RL78 microcontroller SIp SO User device SOp SI CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Remarks 1. 2. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) 2 (5) During communication at same potential (simplified I C mode) (1/2) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. SCLr clock frequency fSCL 2.7 V ≤ EVDD0 ≤ 5.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2 (5) During communication at same potential (simplified I C mode) (2/2) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage main) Mode main) Mode main) Mode MIN. Data setup time (reception) Data hold time (transmission) tSU:DAT tHD:DAT MAX. MIN. MAX. MIN. Unit MAX. 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2 Simplified I C mode mode connection diagram (during communication at same potential) VDD Rb SDA SDAr User device RL78 microcontroller SCLr SCL 2 Simplified I C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD:DAT tSU:DAT Remarks 1. Rb[Ω]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance 2.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high- LS (low-speed LV (lowspeed main) main) Mode voltage main) Mode Mode MIN. Transfer rate Reception 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Theoretical value MAX. MIN. MAX. MIN. Unit MAX.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (highLS (lowLV (lowspeed main) speed main) voltage Mode Mode main) Mode Unit MIN. MAX. MIN. MAX. MIN. MAX. Transfer rate Transmission 4.0 V ≤ EVDD0 ≤ 5.5 V, Note 1 2.7 V ≤ Vb ≤ 4.
RL78/G13 3. 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V ≤ EVDD0 < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V Maximum transfer rate = 1 2.0 {−Cb × Rb × ln (1 − Vb )} × 3 Baud rate error (theoretical value) = [bps] 1 2.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remarks 1. Rb[Ω]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (1/2) (TA = −40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time tKCY1 tKCY1 ≥ 2/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, MAX. LS (low-speed main) Mode MIN. MAX. LV (low-voltage main) Mode MIN.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (2/2) (TA = −40 to +85°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SIp setup time (to SCKp↓) Note 2 tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, MAX. LS (low-speed main) Mode MIN. MAX.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/3) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter SCKp cycle time Symbol tKCY1 Conditions tKCY1 ≥ 4/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode MIN. MIN. MIN. MAX. MAX. Unit MAX.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/3) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter SIp setup time (to SCKp↑) Note 1 Symbol tSIK1 Conditions 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode MIN. MIN. MIN. MAX. MAX. Unit MAX.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (3/3) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter SIp setup time (to SCKp↓) Note 1 Symbol tSIK1 Conditions 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, HS (high-speed main) Mode LS (low-speed main) Mode LV (low-voltage main) Mode MIN. MIN. MIN. MAX. MAX. Unit MAX.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) CSI mode connection diagram (during communication at different potential) Vb Rb Vb Rb SCKp SIp RL78 microcontroller SOp SCK SO User device SI Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol Conditions HS (highLS (low-speed LV (low-voltage Unit main) Mode main) Mode speed main) Mode MIN. SCKp cycle time Note 1 tKCY2 4.0 V ≤ EVDD0 ≤ 5.5 V, 24 MHz < fMCK MAX. MIN. MAX.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Parameter Symbol Conditions HS (highLS (low-speed LV (low-voltage Unit main) Mode main) Mode speed main) Mode MIN. SCKp high-/low-level width SIp setup time (to SCKp↑) Note 3 tKH2, tKL2 tSIK2 MIN. MAX.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) CSI mode connection diagram (during communication at different potential) Vb Rb SCKp RL78 microcontroller SIp SOp SCK SO User device SI Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage 2.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 Output data SOp CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2 (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I C mode) (1/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCLr clock frequency fSCL MAX. MIN. 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 300 Note 1 Note 1 Note 1 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2 (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I C mode) (2/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. Data setup time (reception) Data hold time (transmission) tSU:DAT tHD:DAT MAX. LS (low-speed main) Mode MIN. MAX. LV (low-voltage main) Mode MIN. Unit MAX. 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2 Simplified I C mode connection diagram (during communication at different potential) Vb Vb Rb Rb SDA SDAr RL78 microcontroller User device SCLr SCL 2 Simplified I C mode serial transfer timing (during communication at different potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD:DAT tSU:DAT Remarks 1.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.5.2 Serial interface IICA 2 (1) I C standard mode (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter SCLA0 clock frequency Symbol fSCL Conditions Standard mode: fCLK ≥ 1 MHz HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode MIN. MAX. MIN. MAX. MIN. MAX. 2.7 V ≤ EVDD0 ≤ 5.5 V 0 100 0 100 0 100 kHz 1.8 V ≤ EVDD0 ≤ 5.
RL78/G13 Notes 1. 2. 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection register (PIOR) is 1.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2 (2) I C fast mode (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter SCLA0 clock frequency Symbol fSCL Conditions Fast mode: fCLK ≥ 3.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2 (3) I C fast mode plus (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Fast mode plus: 2.7 V ≤ EVDD0 ≤ 5.5 V fCLK ≥ 10 MHz MIN. MAX. 0 1000 LS (low-speed main) Mode MIN. MAX. LV (low-voltage main) Mode MIN. Unit MAX. ⎯ ⎯ kHz 0.26 ⎯ ⎯ μs 2.7 V ≤ EVDD0 ≤ 5.5 V 0.26 ⎯ ⎯ μs tLOW 2.7 V ≤ EVDD0 ≤ 5.5 V 0.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.6 Analog Characteristics 2.6.1 A/D converter characteristics Classification of A/D converter characteristics Reference Voltage Input channel Reference voltage (+) = AVREFP Reference voltage (−) = AVREFM Reference voltage (+) = VDD Reference voltage (−) = VSS Reference voltage (+) = VBGR Reference voltage (−) = AVREFM ANI0 to ANI14 Refer to 2.6.1 (1). Refer to 2.6.1 (3). Refer to 2.6.1 (4). ANI16 to ANI26 Refer to 2.6.1 (2).
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD. 4.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI16 to ANI26 (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, 1.6 V ≤ AVREFP ≤ VDD ≤ 5.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = VSS (ADREFM = 0), target pin : ANI0 to ANI14, ANI16 to ANI26, internal reference voltage, and temperature sensor output voltage (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VDD, Reference voltage (−) = VSS) Parameter Resolution Symbol Conditions RES Note 1 Overall error AINL MIN. TYP.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) (4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI0, ANI2 to ANI14, ANI16 to ANI26 (TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, 1.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.6.2 Temperature sensor/internal reference voltage characteristics (TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions MIN.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.6.4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = −40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Detection voltage Supply voltage level Symbol VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VLVD8 VLVD9 VLVD10 VLVD11 VLVD12 VLVD13 Minimum pulse width Detection delay time R01DS0131EJ0310 Rev.3.10 Nov 15, 2013 tLW Conditions MIN. TYP. MAX.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) LVD Detection Voltage of Interrupt & Reset Mode (TA = −40 to +85°C, VPDR ≤ VDD ≤ 5.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C, VSS = 0 V) Parameter Data retention supply voltage Symbol Conditions MIN. TYP. Note 1.46 VDDDR MAX. Unit 5.5 V Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected.
RL78/G13 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85°C) 2.10 Timing Specs for Switching Flash Memory Programming Modes (TA = −40 to +85°C, 1.8 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Time to complete the Conditions MIN. TYP. MAX. Unit 100 ms tSUINIT POR and LVD reset must be released before the external reset is released.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105C) This chapter describes the electrical specifications for the products "G: Industrial applications (TA = -40 to +105C)". Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and evaluation.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Remark The electrical characteristics of the products G: Industrial applications (TA = -40 to +105°C) are different from those of the products “A: Consumer applications, and D: Industrial applications”. For details, refer to 3.1 to 3.10. 3.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25°C) (1/2) Parameter Supply voltage Symbols Conditions Ratings Unit VDD −0.5 to +6.5 V EVDD0, EVDD1 EVDD0 = EVDD1 −0.5 to +6.
RL78/G13 3.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.2 Oscillator Characteristics 3.2.1 X1, XT1 oscillator characteristics (TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Resonator X1 clock oscillation frequency (fX)Note Ceramic resonator/ crystal resonator XT1 clock oscillation frequency (fX)Note Crystal resonator Conditions MIN. TYP. MAX. Unit 2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz 2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz 35 kHz 32 32.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.3 DC Characteristics 3.3.1 Pin characteristics (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/5) Items Symbol Output current, highNote 1 IOH1 Conditions Notes 1. TYP. 2.4 V ≤ EVDD0 ≤ 5.5 V Per pin for P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 MAX. -3.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/5) Items Symbol Output current, lowNote 1 IOL1 Conditions MIN. TYP. Unit 8.5 Per pin for P60 to P63 15.0 Note 2 mA mA 4.0 V ≤ EVDD0 ≤ 5.5 V 40.0 mA 2.7 V ≤ EVDD0 < 4.0 V 15.0 mA 2.4 V ≤ EVDD0 < 2.7 V 9.0 mA Total of P05, P06, P10 to P17, P30, 4.0 V ≤ EVDD0 ≤ 5.5 V P31, P50 to P57, P60 to P67, 2.7 V ≤ EVDD0 < 4.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/5) Items Input voltage, high Symbol VIH1 VIH2 Conditions MIN.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (4/5) Items Symbol Output voltage, high Output voltage, low Conditions MIN. TYP. MAX. Unit P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 4.0 V ≤ EVDD0 ≤ 5.5 V, EVDD0 − IOH1 = −3.0 mA 0.7 V 2.7 V ≤ EVDD0 ≤ 5.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (5/5) Items Input leakage current, high Input leakage current, low On-chip pll-up resistance Symbol Conditions MIN. TYP. MAX.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.3.2 Supply current characteristics (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (1/2) Parameter Symbol Supply IDD1 current Note 1 Conditions MIN. TYP. MAX. Unit Operating HS (highfIH = 32 MHz Note 3 mode speed main) mode Note 5 Basic operation VDD = 5.0 V 2.1 VDD = 3.0 V 2.1 Normal operation VDD = 5.0 V 4.6 7.5 VDD = 3.0 V 4.6 7.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = 0 V) (2/2) Parameter Symbol Supply current IDD2 Note 2 Conditions HALT mode Note 1 HS (highspeed main) mode Note 7 Note 4 fIH = 24 MHz Note 4 fIH = 32 MHz fIH = 16 MHz HS (highspeed main) mode Note 7 MIN. Note 4 Note 3 fMX = 20 MHz , VDD = 5.0 V Note 3 fMX = 20 MHz , TYP. MAX. Unit VDD = 5.0 V 0.54 2.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite. 2.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2) Parameter Symbol IDD1 Supply current Note 1 Conditions Operating HS (highfIH = 32 MHz Note 3 mode speed main) mode Note 5 MIN. Basic operation TYP. VDD = 5.0 V 2.3 MAX. Unit mA VDD = 3.0 V 2.3 Normal operation VDD = 5.0 V 5.2 9.2 mA VDD = 3.0 V 5.2 9.2 mA Normal operation VDD = 5.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2) Parameter Symbol Supply current IDD2 Note 2 Conditions HALT mode Note 1 HS (highspeed main) mode Note 7 fIH = 32 MHz Note 4 fIH = 24 MHz Note 4 fIH = 16 MHz HS (highspeed main) mode Note 7 Subsystem clock operation IDD3Note 6 Note 4 MIN. VDD = 5.0 V TYP. MAX. Unit 0.62 3.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the peripheral operation current.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (3) Peripheral Functions (Common to all products) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Low-speed onchip oscillator operating current IFILNote 1 0.20 μA RTC operating current IRTC 0.02 μA 12-bit interval timer operating current IIT Notes 1, 2, 0.02 μA Watchdog timer operating current IWDT 0.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter is in operation. 7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVD when the LVD circuit is in operation. 8. Current flowing only during data flash rewrite. 9. Current flowing only during self programming. 10.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.4 AC Characteristics (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Instruction cycle (minimum instruction execution time) Symbol TCY Conditions Main system clock (fMAIN) operation MIN. TYP. HS (high-speed 2.7 V ≤ VDD ≤ 5.5 V 0.03125 main) mode 2.4 V ≤ VDD < 2.7 V 0.0625 Subsystem clock (fSUB) 2.4 V ≤ VDD ≤ 5.5 V 28.5 30.5 MAX. Unit 1 μs 1 μs 31.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) Cycle time TCY [µs] 10 1.0 When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.1 0.0625 0.05 0.03125 0.01 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 2.4 2.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) TI/TO Timing tTIH tTIL TI00 to TI07, TI10 to TI17 1/fTO TO00 to TO07, TO10 to TO17 Interrupt Request Input Timing tINTH tINTL INTP0 to INTP11 Key Interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET R01DS0131EJ0310 Rev.3.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.5 Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL 3.5.1 Serial array unit (1) During communication at same potential (UART mode) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. Transfer rate Note 1 Theoretical value of the maximum transfer rate fCLK = 32 MHz, fMCK = fCLK Unit MAX.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time tKCY1 SCKp high-/low-level width SIp setup time (to SCKp↑) Note 1 tKH1, tKL1 tSIK1 tKSO1 MAX. tKCY1 ≥ 4/fCLK 2.7 V ≤ EVDD0 ≤ 5.5 V 250 ns 2.4 V ≤ EVDD0 ≤ 5.5 V 500 ns 4.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time Note 5 tKCY2 tKH2, tKL2 MAX. 4.0 V ≤ EVDD0 ≤ 5.5 V 20 MHz < fMCK 16/fMCK ns fMCK ≤ 20 MHz 12/fMCK ns 2.7 V ≤ EVDD0 ≤ 5.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 Output data SOp CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 2 (4) During communication at same potential (simplified I C mode) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCLr clock frequency Hold time when SCLr = “L” Hold time when SCLr = “H” Data setup time (reception) Data hold time (transmission) fSCL tLOW tHIGH tSU:DAT tHD:DAT Unit MAX. 2.7 V ≤ EVDD0 ≤ 5.5 V, Cb = 50 pF, Rb = 2.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 2 Simplified I C mode mode connection diagram (during communication at same potential) VDD Rb SDA SDAr User device RL78 microcontroller SCLr SCL 2 Simplified I C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD:DAT tSU:DAT Remarks 1. Rb[Ω]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance 2.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. Transfer rate Reception 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Theoretical value of the maximum transfer rate fCLK = 32 MHz, fMCK = fCLK 2.7 V ≤ EVDD0 < 4.0 V, Theoretical value of the 2.3 V ≤ Vb ≤ 2.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Unit MIN. Transfer rate Transmission 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V Theoretical value of the maximum transfer rate MAX. Note 1 bps 2.6 Note 2 Mbps Note 3 bps Cb = 50 pF, Rb = 1.4 kΩ, Vb = 2.7 V 2.
RL78/G13 5. 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.4 V ≤ EVDD0 < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V Maximum transfer rate = 1 1.5 {−Cb × Rb × ln (1 − Vb )} × 3 Baud rate error (theoretical value) = [bps] 1 1.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remarks 1. Rb[Ω]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (1/3) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time tKCY1 tKCY1 ≥ 4/fCLK 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Unit MAX.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (2/3) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SIp setup time (to SCKp↑) Note tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Unit MAX. 162 ns 354 ns 958 ns 38 ns 38 ns 38 ns Cb = 30 pF, Rb = 1.4 kΩ 2.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output) (3/3) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SIp setup time (to SCKp↓) Note tSIK1 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Unit MAX. 88 ns 88 ns 220 ns 38 ns 38 ns 38 ns Cb = 30 pF, Rb = 1.4 kΩ 2.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) CSI mode connection diagram (during communication at different potential) Vb Vb Rb Rb SCKp RL78 microcontroller SCK SIp SO SOp SI User device Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCKp cycle time Note 1 tKCY2 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V 2.4 V ≤ EVDD0 < 3.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 Output data SOp CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 2 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I C mode) (1/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. SCLr clock frequency fSCL Unit MAX. 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 400 Note 1 kHz 2.7 V ≤ EVDD0 < 4.0 V, 400 Note 1 kHz 100 Note 1 kHz 2.7 V ≤ EVDD0 < 4.0 V, 2.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 2 (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I C mode) (2/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode MIN. Data setup time (reception) Data hold time (transmission) tSU:DAT tHD:DAT 4.0 V ≤ EVDD0 ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + 340 2.7 V ≤ EVDD0 < 4.0 V, 2.3 V ≤ Vb ≤ 2.
RL78/G13 3.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.5.2 Serial interface IICA (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions HS (high-speed main) Mode Standard Mode SCLA0 clock frequency fSCL Unit Fast Mode MIN. MAX. MIN. MAX. Fast mode: fCLK ≥ 3.5 MHz − − 0 400 kHz Standard mode: fCLK ≥ 1 MHz 0 100 − − kHz tSU:STA 4.7 0.6 μs Hold time tHD:STA 4.0 0.6 μs Hold time when SCLA0 = “L” tLOW 4.7 1.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.6 Analog Characteristics 3.6.1 A/D converter characteristics Classification of A/D converter characteristics Reference Voltage Reference voltage (+) = Reference voltage (+) = VBGR AVREFP Reference voltage (−) = Reference voltage (+) = VDD Reference Input channel AVREFM Reference voltage (−) = VSS AVREFM voltage ANI0 to ANI14 Refer to 3.6.1 (1). Refer to 3.6.1 (3). Refer to 3.6.1 (4). ANI16 to ANI26 Refer to 3.6.1 (2).
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. 3. When AVREFP < VDD, the MAX. values are as follows. Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD. Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD. Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD. 4. Refer to 3.6.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI16 to ANI26 (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, 2.4 V ≤ AVREFP ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V) Parameter Resolution Symbol Conditions RES Note 1 AINL 2.4 V ≤ AVREFP ≤ 5.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = VSS (ADREFM = 0), target pin : ANI0 to ANI14, ANI16 to ANI26, internal reference voltage, and temperature sensor output voltage (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VDD, Reference voltage (−) = VSS) Parameter Symbol Resolution Conditions MIN. RES Note 1 TYP. 8 MAX.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) (4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target pin : ANI0, ANI2 to ANI14, ANI16 to ANI26 (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VBGR Note 3 , Reference voltage (−) = AVREFM Parameter Note 4 = 0 V, HS (high-speed main) mode) Symbol Resolution Conditions MIN. TYP.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.6.2 Temperature sensor/internal reference voltage characteristics (TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode) Parameter Symbol Temperature sensor output voltage VTMPS25 Conditions MIN.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.6.4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = −40 to +105°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Detection voltage Symbol Supply voltage level VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Minimum pulse width Conditions MIN. TYP. MAX. Unit Power supply rise time 3.90 4.06 4.22 V Power supply fall time 3.83 3.98 4.13 V Power supply rise time 3.60 3.75 3.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +105°C, VSS = 0 V) Parameter Symbol Data retention supply voltage Conditions MIN. TYP. Note 1.44 VDDDR MAX. Unit 5.5 V Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected.
RL78/G13 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105°C) 3.10 Timing Specs for Switching Flash Memory Programming Modes (TA = −40 to +105°C, 2.4 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Time to complete the Conditions MIN. TYP. MAX. Unit 100 ms tSUINIT POR and LVD reset must be released before the external reset is released. tSU POR and LVD reset must be released before the external reset is released.
RL78/G13 4. PACKAGE DRAWINGS 4. PACKAGE DRAWINGS 4.1 20-pin Products R5F1006AASP, R5F1006CASP, R5F1006DASP, R5F1006EASP R5F1016AASP, R5F1016CASP, R5F1016DASP, R5F1016EASP R5F1006ADSP, R5F1006CDSP, R5F1006DDSP, R5F1006EDSP R5F1016ADSP, R5F1016CDSP, R5F1016DDSP, R5F1016EDSP R5F1006AGSP, R5F1006CGSP, R5F1006DGSP, R5F1006EGSP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LSSOP20-0300-0.65 PLSP0020JC-A S20MC-65-5A4-3 0.
RL78/G13 4. PACKAGE DRAWINGS 4.2 24-pin Products R5F1007AANA, R5F1007CANA, R5F1007DANA, R5F1007EANA R5F1017AANA, R5F1017CANA, R5F1017DANA, R5F1017EANA R5F1007ADNA, R5F1007CDNA, R5F1007DDNA, R5F1007EDNA R5F1017ADNA, R5F1017CDNA, R5F1017DDNA, R5F1017EDNA R5F1007AGNA, R5F1007CGNA, R5F1007DGNA, R5F1007EGNA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-HWQFN24-4x4-0.50 PWQN0024KE-A P24K8-50-CAB-1 0.
RL78/G13 4. PACKAGE DRAWINGS 4.3 25-pin Products R5F1008AALA, R5F1008CALA, R5F1008DALA, R5F1008EALA R5F1018AALA, R5F1018CALA, R5F1018DALA, R5F1018EALA R5F1008ADLA, R5F1008CDLA, R5F1008DDLA, R5F1008EDLA R5F1018ADLA, R5F1018CDLA, R5F1018DDLA, R5F1018EDLA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-WFLGA25-3x3-0.50 PWLG0025KA-A P25FC-50-2N2-2 0.01 21x b w S A S AB M A ZD D x e ZE 5 4 B 3 2.27 E 2 C 1 E w S B INDEX MARK y1 S D C B A D 2.
RL78/G13 4. PACKAGE DRAWINGS 4.4 30-pin Products R5F100AAASP, R5F100ACASP, R5F100ADASP, R5F100AEASP, R5F100AFASP, R5F100AGASP R5F101AAASP, R5F101ACASP, R5F101ADASP, R5F101AEASP, R5F101AFASP, R5F101AGASP R5F100AADSP, R5F100ACDSP, R5F100ADDSP, R5F100AEDSP, R5F100AFDSP, R5F100AGDSP R5F101AADSP, R5F101ACDSP, R5F101ADDSP, R5F101AEDSP, R5F101AFDSP, R5F101AGDSP R5F100AAGSP, R5F100ACGSP, R5F100ADGSP,R5F100AEGSP, R5F100AFGSP, R5F100AGGSP JEITA Package Code RENESAS Code Previous Code MASS (TYP.
RL78/G13 4. PACKAGE DRAWINGS 4.5 32-pin Products R5F100BAANA, R5F100BCANA, R5F100BDANA, R5F100BEANA, R5F100BFANA, R5F100BGANA R5F101BAANA, R5F101BCANA, R5F101BDANA, R5F101BEANA, R5F101BFANA, R5F101BGANA R5F100BADNA, R5F100BCDNA, R5F100BDDNA, R5F100BEDNA, R5F100BFDNA, R5F100BGDNA R5F101BADNA, R5F101BCDNA, R5F101BDDNA, R5F101BEDNA, R5F101BFDNA, R5F101BGDNA R5F100BAGNA, R5F100BCGNA, R5F100BDGNA,R5F100BEGNA, R5F100BFGNA, R5F100BGGNA JEITA Package Code RENESAS Code Previous Code MASS (TYP.
RL78/G13 4. PACKAGE DRAWINGS 4.6 36-pin Products R5F100CAALA, R5F100CCALA, R5F100CDALA, R5F100CEALA, R5F100CFALA, R5F100CGALA R5F101CAALA, R5F101CCALA, R5F101CDALA, R5F101CEALA, R5F101CFALA, R5F101CGALA R5F100CADLA, R5F100CCDLA, R5F100CDDLA, R5F100CEDLA, R5F100CFDLA, R5F100CGDLA R5F101CADLA, R5F101CCDLA, R5F101CDDLA, R5F101CEDLA, R5F101CFDLA, R5F101CGDLA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-WFLGA36-4x4-0.50 PWLG0036KA-A P36FC-50-AA4-2 0.
RL78/G13 4. PACKAGE DRAWINGS 4.
RL78/G13 4. PACKAGE DRAWINGS 4.
RL78/G13 4. PACKAGE DRAWINGS 4.
RL78/G13 4.
RL78/G13 4. PACKAGE DRAWINGS 4.
RL78/G13 4. PACKAGE DRAWINGS 4.
RL78/G13 4.
RL78/G13 4. PACKAGE DRAWINGS R5F100LCABG, R5F100LDABG, R5F100LEABG, R5F100LFABG, R5F100LGABG, R5F100LHABG, R5F101LDABG, R5F101LEABG, R5F101LFABG, R5F101LGABG, R5F101LHABG, R5F100LDDBG, R5F100LEDBG, R5F100LFDBG, R5F100LGDBG, R5F100LHDBG, R5F101LDDBG, R5F101LEDBG, R5F101LFDBG, R5F101LGDBG, R5F101LHDBG, R5F100LJABG R5F101LCABG, R5F101LJABG R5F100LCDBG, R5F100LJDBG R5F101LCDBG, R5F101LJDBG JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-VFBGA64-4x4-0.
RL78/G13 4. PACKAGE DRAWINGS 4.12 80-pin Products R5F100MFAFA, R5F100MGAFA, R5F100MHAFA, R5F100MJAFA, R5F100MKAFA, R5F100MLAFA R5F101MFAFA, R5F101MGAFA, R5F101MHAFA, R5F101MJAFA, R5F101MKAFA, R5F101MLAFA R5F100MFDFA, R5F100MGDFA, R5F100MHDFA, R5F100MJDFA, R5F100MKDFA, R5F100MLDFA R5F101MFDFA, R5F101MGDFA, R5F101MHDFA, R5F101MJDFA, R5F101MKDFA, R5F101MLDFA R5F100MFGFA, R5F100MGGFA, R5F100MHGFA, R5F100MJGFA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP80-14x14-0.
RL78/G13 4. PACKAGE DRAWINGS R5F100MFAFB, R5F100MGAFB, R5F100MHAFB, R5F100MJAFB, R5F100MKAFB, R5F100MLAFB R5F101MFAFB, R5F101MGAFB, R5F101MHAFB, R5F101MJAFB, R5F101MKAFB, R5F101MLAFB R5F100MFDFB, R5F100MGDFB, R5F100MHDFB, R5F100MJDFB, R5F100MKDFB, R5F100MLDFB R5F101MFDFB, R5F101MGDFB, R5F101MHDFB, R5F101MJDFB, R5F101MKDFB, R5F101MLDFB R5F100MFGFB, R5F100MGGFB, R5F100MHGFB, R5F100MJGFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP80-12x12-0.50 PLQP0080KE-A P80GK-50-8EU-2 0.
RL78/G13 4. PACKAGE DRAWINGS 4.13 100-pin Products R5F100PFAFB, R5F100PGAFB, R5F100PHAFB, R5F100PJAFB, R5F100PKAFB, R5F100PLAFB R5F101PFAFB, R5F101PGAFB, R5F101PHAFB, R5F101PJAFB, R5F101PKAFB, R5F101PLAFB R5F100PFDFB, R5F100PGDFB, R5F100PHDFB, R5F100PJDFB, R5F100PKDFB, R5F100PLDFB R5F101PFDFB, R5F101PGDFB, R5F101PHDFB, R5F101PJDFB, R5F101PKDFB, R5F101PLDFB R5F100PFGFB, R5F100PGGFB, R5F100PHGFB, R5F100PJGFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP100-14x14-0.
RL78/G13 4. PACKAGE DRAWINGS R5F100PFAFA, R5F100PGAFA, R5F100PHAFA, R5F100PJAFA, R5F100PKAFA, R5F100PLAFA R5F101PFAFA, R5F101PGAFA, R5F101PHAFA, R5F101PJAFA, R5F101PKAFA, R5F101PLAFA R5F100PFDFA, R5F100PGDFA, R5F100PHDFA, R5F100PJDFA, R5F100PKDFA, R5F100PLDFA R5F101PFDFA, R5F101PGDFA, R5F101PHDFA, R5F101PJDFA, R5F101PKDFA, R5F101PLDFA R5F100PFGFA, R5F100PGGFA, R5F100PHGFA, R5F100PJGFA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP100-14x20-0.65 PLQP0100JC-A P100GF-65-GBN-1 0.
RL78/G13 4. PACKAGE DRAWINGS 4.14 128-pin Products R5F100SHAFB, R5F100SJAFB, R5F100SKAFB, R5F100SLAFB R5F101SHAFB, R5F101SJAFB, R5F101SKAFB, R5F101SLAFB R5F100SHDFB, R5F100SJDFB, R5F100SKDFB, R5F100SLDFB R5F101SHDFB, R5F101SJDFB, R5F101SKDFB, R5F101SLDFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP128-14x20-0.50 PLQP0128KD-A P128GF-50-GBP-1 0.
Revision History RL78/G13 Data Sheet Description Rev. Date Page 1.00 Feb 29, 2012 - First Edition issued 2.00 Oct 12, 2012 7 Figure 1-1. Part Number, Memory Size, and Package of RL78/G13: Pin count corrected. 25 1.4 Pin Identification: Description of pins INTP0 to INTP11 corrected. 40, 42, 44 1.6 Outline of Functions: Descriptions of Subsystem clock, Low-speed on-chip oscillator, and General-purpose register corrected. 41, 43, 45 1.6 Outline of Functions: Lists of Descriptions changed.
Description Summary Rev. Date Page 3.
Description Summary Rev. Date Page 3.00 Aug 02, 2013 118 Modification of table in 2.6.2 Temperature sensor/internal reference voltage characteristics 118 Modification of table and note in 2.6.3 POR circuit characteristics 119 Modification of table in 2.6.4 LVD circuit characteristics 120 Modification of table of LVD Detection Voltage of Interrupt & Reset Mode 120 Renamed to 2.6.5 Power supply voltage rising slope characteristics 122 Modification of table, figure, and remark in 2.
Rev. Date Page 3.00 Aug 02, 2013 163 164, 165 Nov 15, 2013 Modification of table in (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2) Modification of table, note 1, and caution in (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2) 166 Modification of table in 3.5.2 Serial interface IICA 166 Modification of IICA serial transfer timing 167 Addition of table in 3.6.1 A/D converter characteristics 167, 168 3.
NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2.