Datasheet
RL78/G13  2. ELECTRICAL SPECIFICATIONS (A, D: T
A = -40 to +85°C) 
Page 86 of 194R01DS0131EJ0310 Rev.3.10 
Nov 15, 2013 
(4)  During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (2/2) 
 (TA = −40 to +85°C, 1.6 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) 
Parameter Symbol  Conditions  HS (high-speed 
main) Mode 
LS (low-speed main) 
Mode 
LV (low-voltage main) 
Mode 
Unit
MIN. MAX. MIN.  MAX.  MIN.  MAX. 
SIp setup time 
(to SCKp↑) 
Note 
1
t
SIK2 2.7 V ≤ EVDD0 ≤ 5.5 V  1/fMCK+2
0 
 1/fMCK+30  1/fMCK+3
0 
 ns
1.8 V ≤ EVDD0 ≤ 5.5 V  1/fMCK+3
0 
 1/fMCK+30  1/fMCK+3
0 
 ns
1.7 V ≤ EVDD0 ≤ 5.5 V  1/fMCK+4
0 
 1/fMCK+40  1/fMCK+4
0 
 ns
1.6 V ≤ EVDD0 ≤ 5.5 V  ⎯ 1/fMCK+40  1/fMCK+4
0 
 ns
SIp hold time 
(from SCKp↑) 
Note 2
t
KSI2 1.8 V ≤ EVDD0 ≤ 5.5 V  1/fMCK+3
1 
 1/fMCK+31  1/fMCK+3
1 
 ns
1.7 V ≤ EVDD0 ≤ 5.5 V  1/fMCK+
250 
 1/fMCK+
250 
 1/fMCK+ 
250 
 ns
1.6 V ≤ EVDD0 ≤ 5.5 V  ⎯ 1/fMCK+
250 
 1/fMCK+ 
250 
 ns
Delay time 
from SCKp↓ to 
SOp output 
Note 
3
t
KSO2  C = 30 
pF 
Note 4
2.7 V ≤ EV
DD0 ≤ 5.5 V   2/fMCK+
44 
 2/fMCK+ 
110 
 2/fMCK+
110 
ns
2.4 V ≤ EVDD0 ≤ 5.5 V   2/fMCK+
75 
 2/fMCK+ 
110 
 2/fMCK+
110 
ns
1.8 V ≤ EVDD0 ≤ 5.5 V   2/fMCK+
110 
 2/fMCK+ 
110 
 2/fMCK+
110 
ns
1.7 V ≤ EVDD0 ≤ 5.5 V   2/fMCK+
220 
 2/fMCK+ 
220 
 2/fMCK+
220 
ns
1.6 V ≤ EVDD0 ≤ 5.5 V   ⎯ 2/fMCK+ 
220 
 2/fMCK+
220 
ns
Notes  1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to 
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 
 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from 
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 
 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output 
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 
 4. C is the load capacitance of the SOp output lines. 
  5. Transfer rate in the SNOOZE mode: MAX. 1 Mbps 
Caution  Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the 
SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). 
Remarks  1.  p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1),  
n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 4, 5, 8, 14) 
 2. f
MCK: Serial array unit operation clock frequency 
    (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,  
n: Channel number (mn = 00 to 03, 10 to 13)) 










