Datasheet

Section 10 I/O Ports
Page 540 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
• P16/PO14/TIOCA2/SSCK0-A
The pin function is switched as shown below according to the combination of the TPU channel
2 settings (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1
and CCLR0 in TCR_2), bit NDER14 in NDERH of PPG, bits MSS and SCKS in SSCRH and
bit SSUMS in SSCRL of SSU, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit P16DDR.
SSU settings (1) in table below (2) in table
below
(3) in table
below
TPU channel 2
settings
(1) in table
below
(2) in table below ⎯
P16DDR ⎯ 0 1 1 0*
4
1
NDER14 ⎯ ⎯ 0 1 ⎯
P16 input P16 output PO14 outputPin function TIOCA2
output
TIOCA2 input
*
1
SSCK0-A
input*
2
*
5
SSCK0-A
output*
3
*
5
TPU channel 2
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011
IOA3 to IOA0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00 Other than B'xx00
CCLR1,
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'01
B'01
Output function ⎯ Output
compare
output
⎯ PWM*
2
mode
1 output
PWM mode
2 output
⎯
[Legend]
x: Don't care
Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1.
2. When using as SSCK0-A input, set SSCK0S1 and SSCK0S0 in PFCR5 to B'00 before
other register setting.
3. When using as SSCK0-A output, set SSCK0S1 and SSCK0S0 in PFCR5 to B'00 before
other register setting.
4. P16DDR = 0 when the SSU pin is used as input.
5. Do not set up for SSU unless SSCK0S1 and SSCK0S0 = B'00 in PFCR5.
Use as I/O port or TPU pin.