Datasheet

Section 16 USB Function Module (USB)
R01UH0309EJ0500 Rev. 5.00 Page 969 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
16.3.22 FIFO Clear Register 0 (FCLR0)
FCLR0 is a register to initialize the FIFO buffers for endpoint 0. Writing 1 to a bit clears all the
data in the corresponding FIFO buffer. Note that the corresponding interrupt flag is not cleared.
Do not clear a FIFO buffer during transfer.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
⎯
⎯
⎯
⎯
⎯
⎯
0
0
0
0
0
0
⎯
⎯
⎯
⎯
⎯
⎯
Reserved
The write value should always be 0.
1 EP0o CLR 0 W EP0o Clear
Writing 1 to this bit initializes the endpoint 0 receive
FIFO buffer.
0 EP0i CLR 0 W EP0i Clear
Writing 1 to this bit initializes the endpoint 0 transmit
FIFO buffer.