Datasheet

Section 16 USB Function Module (USB)
Page 968 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
16.3.21 Trigger Register 1 (TRG1)
TRG1 generates one-shot triggers to control the transfer sequence for each endpoint.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
⎯
⎯
⎯
⎯
⎯
0
0
0
0
0
⎯
⎯
⎯
⎯
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
2
EP3 PKTE 0 W EP3 Packet Enable
After one packet of data has been written to the
endpoint 3 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
1
EP2 PKTE 0 W EP2 Packet Enable
After one packet of data has been written to the
endpoint 2 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
0
EP1 RDFN 0 W EP1 Read Complete
Write 1 to this bit after one packet of data has been
read from the endpoint 1 FIFO buffer. The endpoint 1
receive FIFO buffer has a dual-buffer configuration.
Writing 1 to this bit initializes the FIFO that was read,
enabling the next packet to be received.