Datasheet

Section 16 USB Function Module (USB)
Page 964 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
16.3.15 EP3 Data Register (EPDR3)
EPDR3 is a 16-byte transmit FIFO buffer for endpoint 3. EPDR3 holds one packet of transmit data
for the interrupt transfer of endpoint 3. Transmit data is fixed by writing one packet of data and
setting EP3 PKTE in trigger register 1. This FIFO buffer can be initialized by means of EP3 CLR
in FCLR register 1.
Bit Bit Name
Initial
Value R/W Description
7 to 0 D7 to D0 Undefined W Data register for endpoint 3 transfer
16.3.16 EP0o Receive Data Size Register (EPSZ0o)
EPSZ0o indicates the number of bytes received at endpoint 0 from the host.
Bit Bit Name
Initial
Value R/W Description
7 to 5 ⎯ All 0 ⎯ Reserved
These bits are always read as 0.
4 to 0 D4 to D0 All 0 R Number of receive data for endpoint 0
16.3.17 EP1 Receive Data Size Register (EPSZ1)
EPSZ1 is a receive data size resister for endpoint 1. EPSZ1 indicates the number of bytes received
from the host. The FIFO for endpoint 1 has a dual-buffer configuration. The size of the received
data indicated by this register is the size of the currently selected side (can be read by CPU).
Bit Bit Name
Initial
Value R/W Description
7 ⎯ 0 ⎯ Reserved
This bit is always read as 0.
6 to 0 D6 to D0 All 0 R Number of received bytes for endpoint 1