Datasheet

Section 16 USB Function Module (USB)
R01UH0309EJ0500 Rev. 5.00 Page 963 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
16.3.13 EP1 Data Register (EPDR1)
EPDR1 is a 128-byte receive FIFO buffer for endpoint 1. EPDR1 has a dual-buffer configuration,
and has a capacity of twice the maximum packet size. When one packet of data is received
successfully, EP1 FULL in interrupt flag register 2 is set, and the number of receive bytes is
indicated in the EP1 receive data size register. After the data has been read, the buffer that was
read is enabled to receive data again by writing 1 to the EP1 RDFN bit in trigger register 1. The
receive data in this FIFO buffer can be transferred by DMA. This FIFO buffer can be initialized
by means of EP1 CLR in FCLR register 1.
Bit Bit Name
Initial
Value R/W Description
7 to 0 D7 to D0 All 0 R Data register for endpoint 1 transfer
16.3.14 EP2 Data Register (EPDR2)
EPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. EPDR2 has a dual-buffer configuration,
and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO
buffer and EP2 PKTE in trigger register 1 is set, one packet of transmit data is fixed, and the dual-
FIFO buffer is switched over. The transmit data for this FIFO buffer can be transferred by DMA.
This FIFO buffer can be initialized by means of EP2 CLR in FCLR register 1.
Bit Bit Name
Initial
Value R/W Description
7 to 0 D7 to D0 Undefined W Data register for endpoint 2 transfer