Datasheet

Section 16 USB Function Module (USB)
Page 962 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
16.3.11 EP0o Data Register (EPDR0o)
EPDR0o is a 16-byte receive FIFO buffer for endpoint 0. EPDR0o holds endpoint 0 receive data
other than setup commands. When data is received successfully, EP0o TS in interrupt flag register
1 is set, and the number of receive bytes is indicated in the EP0o receive data size register. After
the data has been read, setting EP0o RDFN in trigger register 0 enables the next packet to be
received. This FIFO buffer can be initialized by means of EP0o CLR in FCLR register 0.
Bit Bit Name
Initial
Value R/W Description
7 to 0 D7 to D0 All 0 R Data register for control-out transfer
16.3.12 EP0s Data Register (EPDR0s)
EPDR0s is an 8-byte FIFO buffer specifically for receiving endpoint 0 setup commands. Only the
setup command to be processed by the application is received. When command data is received
successfully, the SETUPTS bit in interrupt flag register 1 is set.
As a latest setup command must be received in high priority, if data is left in this buffer, it will be
overwritten with new data. If reception of the next command is started while the current command
is being read, command reception has priority, the read by the application is forcibly stopped, and
the read data is invalid.
Bit Bit Name
Initial
Value R/W Description
7 to 0 D7 to D0 All 0 R Data register for storing the setup command at the
control-out transfer