Datasheet

Section 16 USB Function Module (USB)
R01UH0309EJ0500 Rev. 5.00 Page 961 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
16.3.9 Interrupt Select Register 2 (ISR2)
ISR2 selects the vector numbers of the interrupt requests indicated in interrupt flag register 2
(IFR2). If the USB issues an interrupt request to the INTC when a bit in ISR2 is cleared to 0, the
interrupt corresponding to the bit will be USBINTN2. If the USB issues an interrupt request to the
INTC when a bit in ISR2 is set to 1, the corresponding interrupt will be USBINTN3.
Bit Bit Name
Initial
Value R/W Description
7
6
⎯
⎯
0
0
⎯
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
5 EP3 TRS 0 R/W EP3 Transfer Request
4 EP3 TSS 0 R/W EP3 Transmission Complete
3 EP2 TRS 0 R/W EP2 Transfer Request
2 EP2
EMPTYS
0 R/W EP2 FIFO Empty
1 EP2
ALLEMPS
0 R/W EP2 FIFO All Empty
0 EP1 FULLS 0 R/W EP1 FIFO Full
16.3.10 EP0i Data Register (EPDR0i)
EPDR0i is a 16-byte transmit FIFO buffer for endpoint 0. EPDR0i holds one packet of transmit
data for control-in. Transmit data is fixed by writing one packet of data and setting EP0i PKTE in
trigger register 0. When an ACK handshake is returned from the host after the data has been
transmitted, EP0i TS in interrupt flag register 1 is set. This FIFO buffer can be initialized by
means of EP0i CLR in FCLR register 0.
Bit Bit Name
Initial
Value R/W Description
7 to 0 D7 to D0 Undefined W Data register for control-in transfer