Datasheet

Section 16 USB Function Module (USB)
R01UH0309EJ0500 Rev. 5.00 Page 957 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
16.3.5 Interrupt Enable Register 1 (IER1)
IER1 enables the interrupt requests of interrupt flag register 1 (IFR1). When an interrupt flag is set
to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the
CPU. The interrupt vector number is determined by the contents of interrupt select register 1
(ISR1).
Bit Bit Name
Initial
Value R/W Description
7
6
5
⎯
⎯
⎯
0
0
0
⎯
⎯
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
4 SOFE 0 R/W SOF Packet Detection
3 SETUP TSE 0 R/W Setup Command Receive Complete
2 EP0o TSE 0 R/W EP0o Receive Complete
1 EP0i TRE 0 R/W EP0i Transfer Request
0 EP0i TSE 0 R/W EP0i Transmission Complete