Datasheet

Section 16 USB Function Module (USB)
Page 956 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Bit Bit Name
Initial
Value R/W Description
0 EP1 FULL 0 R EP1 FIFO Full
This bit is set when endpoint 1 receives one packet of
data successfully from the host, and holds a value of 1
as long as there is valid data in the FIFO buffer.
This is a status bit and cannot be cleared.
16.3.4 Interrupt Enable Register 0 (IER0)
IER0 enables the interrupt requests of interrupt flag register 0 (IFR0). When an interrupt flag is set
to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the
CPU. The interrupt vector number is determined by the contents of interrupt select register 0
(ISR0).
Bit Bit Name
Initial
Value R/W Description
7 BRSTE 0 R/W Bus Reset
6 CFDNE 0 R/W End Point Information Load End
5 SSRSME 0 R/W Resume Detection for Software Standby Cancel
For details of the operation, see section 16.5.4,
Suspend and Resume Operations.
4 SURSFE 0 R/W Suspend/Resume Detection
For details of the operation, see section 16.5.4,
Suspend and Resume Operations.
3 SETCE 0 R/W Set_Configuration Command Detection
2 SETIE 0 R/W Set_Interface Command Detection
1 ⎯ 0 ⎯ Reserved
This bit is always read as 0. The write value should
always be 0.
0 VBUSFE 0 R/W USB Bus Connection/Disconnection