Datasheet

Section 16 USB Function Module (USB)
R01UH0309EJ0500 Rev. 5.00 Page 955 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
16.3.3 Interrupt Flag Register 2 (IFR2)
IFR2, together with interrupt flag registers 0 and 1, (IFR0 and IFR1), indicates interrupt status
information required by the application. When an interrupt source is generated, the corresponding
bit is set to 1. And then this bit, in combination with interrupt enable register 2 (IER2), generates
an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
However, since EP2 EMPTY, EP2 ALLEMP, and EP1 FULL are status bits, these bits cannot be
cleared.
Bit Bit Name
Initial
Value R/W Description
7
6
⎯
⎯
0
0
⎯
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
5 EP3 TR 0 R/W EP3 Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 3 is
received from the host. A NAK handshake is returned
to the host until data is written to the FIFO buffer and
packet transmission is enabled.
4 EP3 TS 0 R/W EP3 Transmit Complete
This bit is set when data is transmitted to the host from
endpoint 3 and an ACK handshake is returned.
3 EP2 TR 0 R/W EP2 Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 2 is
received from the host. A NAK handshake is returned
to the host until data is written to the FIFO buffer and
packet transmission is enabled.
2 EP2 EMPTY 1 R EP2 FIFO Empty
This bit is set when at least one of the dual endpoint 2
transmit FIFO buffers is ready for transmit data to be
written.
This is a status bit and cannot be cleared.
1 EP2
ALLEMP
1 R EP2 FIFO All Empty
This bit is set when both of the dual endpoint 2 transmit
FIFO buffers are empty.
This is a status bit and cannot be cleared.