Datasheet

Section 16 USB Function Module (USB)
Page 954 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
16.3.2 Interrupt Flag Register 1 (IFR1)
IFR1, together with interrupt flag registers 0 and 2 (IFR0 and IFR2), indicates interrupt status
information required by the application. When an interrupt source is generated, the corresponding
bit is set to 1. And then this bit, in combination with interrupt enable register 1 (IER1), generates
an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
Bit Bit Name
Initial
Value R/W Description
7
6
5
⎯
⎯
⎯
0
0
0
⎯
⎯
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
4 SOF 0 R/W SOF Packet Detection
This bit is set to 1 when the Start Of Frame (SOF)
packet is detected.
3 SETUP TS 0 R/W Setup Command Receive Complete
This bit is set to 1 when endpoint 0 receives
successfully a setup command requiring decoding on
the application side, and returns an ACK handshake to
the host.
2 EP0o TS 0 R/W EP0o Receive Complete
This bit is set to 1 when endpoint 0 receives data from
the host successfully, stores the data in the FIFO
buffer, and returns an ACK handshake to the host.
1 EP0i TR 0 R/W EP0i Transfer Request
This bit is set if there is no valid transmit data in the
FIFO buffer when an IN token for endpoint 0 is
received from the host. A NAK handshake is returned
to the host until data is written to the FIFO buffer and
packet transmission is enabled.
0 EP0i TS 0 R/W EP0i Transmit Complete
This bit is set when data is transmitted to the host from
endpoint 0 and an ACK handshake is returned.