Datasheet

Section 16 USB Function Module (USB)
Page 952 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
• Transceiver test register 0 (TRNTREG0)
• Transceiver test register 1 (TRNTREG1)
16.3.1 Interrupt Flag Register 0 (IFR0)
IFR0, together with interrupt flag registers 1 and 2 (IFR1 and IFR2), indicates interrupt status
information required by the application. When an interrupt source is generated, the corresponding
bit is set to 1. And then this bit, in combination with interrupt enable register 0 (IER0), generates
an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
However, since SURSS and VBUSMN are status bits, these bits cannot be cleared.
Bit Bit Name
Initial
Value R/W Description
7 BRST 0 R/W Bus Reset
This bit is set to 1 when a bus reset signal is detected on
the USB bus.
6 CFDN 0 R/W End Point Information Load End
This bit is set to 1 when writing data in the endpoint
information register to the EPIR register ends (load end).
This module starts the USB operation after the endpoint
information is completely set.
5 SURSS 0 R Suspend/Resume Status
This is a status bit that describes bus state.
0: Normal state
1: Suspended state
This is a status bit and cannot be cleared. It generates
no interrupt request.
4 SURSF 0 R/W Suspend/Resume Detection
This bit is set to 1 when the state changed from normal
to suspended state or vice versa. The corresponding
interrupt output is RESUME, USBINTN2, and
USBINTN3.
3 SETC 0 R/W Set_Configuration Command Detection
When the Set_Configuration command is detected, this
bit is set to 1.