Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)

R01UH0309EJ0500 Rev. 5.00 Page 943 of 1408

Sep 24, 2012

H8S/2456, H8S/2456R, H8S/2454 Group

15.10.5 Relation between Writes to TDR and the TDRE Flag

The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from

TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.

Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is

written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has

not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1

before writing transmit data to TDR.

15.10.6 Restrictions on Use of DMAC or DTC

• When an external clock source is used as the serial clock, the transmit clock should not be

input until at least 5 φ clock cycles after TDR is updated by the DMAC or DTC. Incorrect

operation may occur if the transmit clock is input within 4 φ clocks after TDR is updated.

(Figure 15.35)

• When RDR is read by the DMAC or DTC, be sure to set the activation source to the relevant

SCI receive-data-full interrupt (RXI).

LSB

Serial data

SCK

D1 D3 D4 D5D2 D6 D7

Note: When operating on an external clock, set t > 4 clocks.

TDRE

Figure 15.35 Example of Synchronous Transmission Using DTC