Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)
Page 924 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
15.7.4 Receive Data Sampling Timing and Reception Margin
Only the internal clock generated by the on-chip baud rate generator is used as transmit/receive
clock in Smart Card interface. In Smart Card interface mode, the SCI operates on a basic clock
with a frequency of 32, 64, 372, 256, 93, 128, 186, or 512 times the bit rate (fixed at 16 times in
normal asynchronous mode) as determined by bits BCP2 to BCP0. In reception, the SCI samples
the falling edge of the start bit using the basic clock, and performs internal synchronization. As
shown in figure 15.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, 128th,
46th, 64th, 93rd, or 256th pulse of the basic clock, data can be latched at the middle of the bit. The
reception margin is given by the following formula.
M = ⏐ (0.5 – ) – (L – 0.5) F – (1 + F) ⏐ × 100 [%]
1
2N
⏐
D – 0.5
⏐
N
Where M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, 256, 93, 128, 186, or 512)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
M = (0.5 – 1/2 × 372) × 100%
= 49.866%