Datasheet

Section 14 Watchdog Timer (WDT)
R01UH0309EJ0500 Rev. 5.00 Page 853 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
TCNT count
H'00
Time
H'FF
WT/IT=1
TME=1
H'00 written
to TCNT
WT/IT=1
TME=1
H'00 written
to TCNT
132 states
*
2
518 states
WDTOVF signal
Internal reset signal
*
1
Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated.
2. 130 states when the RSTE bit is cleared to 0.
Overflow
WDTOVF and
internal reset are
generated
WOVF=1
Figure 14.2 Operation in Watchdog Timer Mode