Datasheet
Section 13 8-Bit Timers (TMR)
R01UH0309EJ0500 Rev. 5.00 Page 841 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
13.8 Usage Notes
13.8.1 Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T
2
state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed. Figure 13.11 shows
this operation.
A
ddress
φ
TCNT address
Internal write signal
Counter clear signal
TCNT
NH'00
T
1
T
2
TCNT write cycle by CPU
Figure 13.11 Contention between TCNT Write and Clear