Datasheet

Section 13 8-Bit Timers (TMR)
R01UH0309EJ0500 Rev. 5.00 Page 837 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
13.5.4 Timing of Compare Match Clear
TCNT is cleared when compare match A or B occurs, depending on the settings of the CCLR1
and CCLR0 bits in TCR and the TMRIS bit in TCCR. Figure 13.8 shows the timing of this
operation.
NH'00
Compare match
signal
φ
TCNT
Figure 13.8 Timing of Compare Match Clear
13.5.5 Timing of TCNT External Reset
TCNT is cleared at the rising edge, falling edge, low level, or high level of an external reset input,
depending on the settings of the CCLR1 and CCLR0 bits in TCR and the TMRIS bit in TCCR.
The clear pulse width must be at least 1.5 states for a single edge and at least 2.5 states for both
edges. Figure 13.9 shows the timing of this operation.
Clear signal
External reset
input pin
φ
TCNT N H'00N – 1
Figure 13.9 Timing of Clearance by External Reset