Datasheet

Section 13 8-Bit Timers (TMR)
Page 836 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs
The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the
TCOR and TCNT values match. The compare match signal is generated at the last state in which
the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT
match, the compare match signal is not generated until the next incrementation clock input. Figure
13.6 shows this timing.
TCNT
φ
N N + 1
TCOR N
Compare match
signal
CMF
Figure 13.6 Timing of CMF Setting
13.5.3 Timing of Timer Output when Compare-Match Occurs
When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in
TCSR. Figure 13.7 shows the timing when the output is set to toggle at compare match A.
Compare match A
signal
φ
Timer output pin
Figure 13.7 Timing of Timer Output