Datasheet

Section 13 8-Bit Timers (TMR)
Page 830 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Bit Bit Name Initial Value R/W Description
5 OVF 0 R/(W)
*
Timer Overflow Flag
[Setting condition]
Set when TCNT overflows from H'FF to H'00
[Clearing condition]
Cleared by reading OVF when OVF = 1, then
writing 0 to OVF
4 ADTE 0 R/W A/D Trigger Enable
Selects enabling or disabling of A/D converter
start requests by compare match A.
0: A/D converter start requests by compare match
A are disabled
1: A/D converter start requests by compare match
A are enabled
3
2
OS3
OS2
0
0
R/W
R/W
Output Select 3 and 2
These bits select a method of TMO pin output
when compare match B of TCORB and TCNT
occurs.
00: No change when compare match B occurs
01: 0 is output when compare match B occurs
10: 1 is output when compare match B occurs
11: Output is inverted when compare match B
occurs (toggle output)
1
0
OS1
OS0
0
0
R/W
R/W
Output Select 1 and 0
These bits select a method of TMO pin output
when compare match A of TCORA and TCNT
occurs.
00: No change when compare match A occurs
01: 0 is output when compare match A occurs
10: 1 is output when compare match A occurs
11: Output is inverted when compare match A
occurs (toggle output)
Note: Only 0 can be written to, to clear these flags.