Datasheet

Section 2 CPU
Page 56 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
SP (ER7)
Free area
Stack area
Figure 2.8 Stack
2.4.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0.)
2.4.3 Extended Register (EXR)
EXR is an 8-bit register that can be manipulated by the LDC, STC, ANDC, ORC, and XORC
instructions. When these instructions except for the STC instruction is executed, all interrupts
including NMI will be masked for three states after execution is completed.
Bit Bit Name Initial Value R/W Description
7 T 0 R/W Trace Bit
When this bit is set to 1, a trace exception is
started each time an instruction is executed.
When this bit is cleared to 0, instructions are
executed in sequence.
6 to 3 ⎯ All 1 ⎯ Reserved
These bits are always read as 1.
2
1
0
I2
I1
I0
1
1
1
R/W
R/W
R/W
These bits designate the interrupt mask level (0
to 7). For details, see section 5, Interrupt
Controller.