Datasheet

Section 12 Programmable Pulse Generator (PPG)
Page 804 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
• NDRHL*
Bit Bit Name Initial Value R/W Description
7 to 4 ⎯ All 1 ⎯ Reserved
1 is always read and write is disabled.
3
2
1
0
NDR11
NDR10
NDR9
NDR8
0
0
0
0
R/W
R/W
R/W
R/W
Next Data Register 11 to 8
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
• NDRL (NDRLH, NDRLL)*
If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
0
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Next Data Register 7 to 0
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
If pulse output groups 0 and 1 have different output triggers, upper 4 bits and lower 4 bits are
mapped to the different addresses as shown below.