Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
R01UH0309EJ0500 Rev. 5.00 Page 795 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
11.10.12 Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T
2
state of a TCNT write cycle, when
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 11.54 shows the operation timing when there is contention between TCNT write and
overflow.
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T
1
T
2
H'FFFF M
TCNT write data
TCFV flag
Figure 11.54 Contention between TCNT Write and Overflow
11.10.13 Multiplexing of I/O Pins
In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin
with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, the TCLKD input pin
with the TIOCB2 I/O pin, the TCLKE input pin with the TIOCC6 I/O pin, the TCLKF input pin
with the TIOCD6 I/O pin, the TCLKG input pin with the TIOCB7 I/O pin, and the TCLKH input
pin with the TIOCB8 I/O pin. When an external clock is input, compare match output should not
be performed from a multiplexed pin.
11.10.14 Interrupts and Module Stop State
If a transition is made to the module stop state when an interrupt has been requested, it will not be
possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts
should therefore be disabled before entering the module stop state.