Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
R01UH0309EJ0500 Rev. 5.00 Page 793 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
11.10.10 Contention between Buffer Register Write and Input Capture
If the input capture signal is generated in the T
2
state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 11.52 shows the timing in this case.
Input capture
signal
Write signal
Address
φ
TCNT
Buffer register write cycle
T
1
T
2
N
TGR
N
M
M
Buffer
register
Buffer register
address
Figure 11.52 Contention between Buffer Register Write and Input Capture