Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
R01UH0309EJ0500 Rev. 5.00 Page 791 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
11.10.8 Contention between TGR Read and Input Capture
If the input capture signal is generated in the T
1
state of a TGR read cycle, the data that is read will
be the data after input capture transfer.
Figure 11.50 shows the timing in this case.
Input capture
signal
Read signal
Address
φ
TGR address
TGR
TGR read cycle
T
1
T
2
M
Internal
data bus
X M
Figure 11.50 Contention between TGR Read and Input Capture