Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Page 788 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
11.10.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in the T
2
state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented. Figure 11.47 shows the timing in this case.
TCNT input
clock
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T
1
T
2
NM
TCNT write data
Figure 11.47 Contention between TCNT Write and Increment Operations