Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
R01UH0309EJ0500 Rev. 5.00 Page 785 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
(4) Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or
DMAC is activated, the flag is cleared automatically. Figure 11.43 shows the timing for status flag
clearing by the CPU, and figure 11.44 shows the timing for status flag clearing by the DTC or
DMAC.
Status flag
Write signal
Address
TSR address
Interrupt
request
signal
TSR write cycle
T
1
T
2
φ
Figure 11.43 Timing for Status Flag Clearing by CPU
Interrupt
request
signal
Status flag
Address
Source address
DTC/DMAC
read cycle
T
1
T
2
Destination
address
T
1
T
2
DTC/DMAC
write cycle
φ
Figure 11.44 Timing for Status Flag Clearing by DTC/DMAC Activation