Datasheet

Section 2 CPU
R01UH0309EJ0500 Rev. 5.00 Page 47 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Execution States
Instruction Mnemonic H8S/2600 H8S/2000
MULXU MULXU.B Rs, Rd 2* 12
MULXU.W Rs, ERd 2* 20
MULXS MULXS.B Rs, Rd 3* 13
MULXS.W Rs, ERd 3* 21
CLRMAC CLRMAC 1*
LDMAC LDMAC ERs, MACH 1*
LDMAC ERs, MACL 1*
STMAC STMAC MACH, ERd 1*
STMAC MACL, ERd 1*
Not supported
Note: * The number of execution states is incremented following a MAC instruction.
In addition, there are differences in address space, CCR and EXR register functions,
power-down modes, etc., depending on the model.
2.1.2 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements.
• More general registers and control registers
Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been
added.
• Expanded address space
Normal mode supports the same 64-Kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide instructions have been added.
A multiply-and-accumulate instruction has been added.
Two-bit shift and rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.