Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Page 734 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
11.3.5 Timer Status Register (TSR)
TSR registers indicate the status of each channel. The TPU has six TSR registers, one for each
channel.
Bit Bit Name Initial value R/W Description
7 TCFD 1 R Count Direction Flag
Status flag that shows the direction in which TCNT
counts in channels 1, 2, 4, and 5.
In channels 0 and 3, bit 7 is reserved. It is always
read as 1 and cannot be modified.
0: TCNT counts down
1: TCNT counts up
6 ⎯ 1 ⎯ Reserved
This bit is always read as 1 and cannot be
modified.
5 TCFU 0 R/(W)
*
1
Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1, 2, 4, and 5 are set to
phase counting mode.
In channels 0 and 3, bit 5 is reserved. It is always
read as 0 and cannot be modified.
[Setting condition]
When the TCNT value underflows (changes from
H'0000 to H'FFFF)
[Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
4 TCFV 0 R/(W)
*
1
Overflow Flag
Status flag that indicates that TCNT overflow has
occurred.
[Setting condition]
When the TCNT value overflows (changes from
H'FFFF to H'0000)
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1