Datasheet

Section 2 CPU
Page 46 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
• High-speed operation
All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract: 1 state
8 × 8-bit register-register multiply: 2 states
16 ÷ 8-bit register-register divide: 12 states
16 × 16-bit register-register multiply: 3 states
32 ÷ 16-bit register-register divide: 20 states
• Two CPU operating modes
Normal mode
*
Advanced mode
Note: * Normal mode is not available in this LSI.
• Power-down state
Transition to power-down state by SLEEP instruction
CPU clock speed selection
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• The number of execution states of the MULXU and MULXS instructions