Datasheet

Section 10 I/O Ports
R01UH0309EJ0500 Rev. 5.00 Page 681 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
• PH0/CS4/RAS4/WE*
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS4E in
PFCR0, and bit PH0DDR.
Operating
mode
1, 2, 4 3, 7
EXPE ⎯ 0 1
CS4E 0 1 ⎯ 0 1
RMTS2 to
RMTS0
⎯ Area 4 is
normal space
Area 4
is
DRAM
space
Areas 2
to 5 are
syn-
chronous
DRAM
space
⎯ ⎯ Area 4 is
normal space
Area 4
is
DRAM
space
Areas 2
to 5 are
syn-
chronous
DRAM
space
PH0DDR 0 1 0 1 ⎯ ⎯ 0 1 0 1 0 1 ⎯ ⎯
Pin
function
PH0
input
PH0
output
PH0
input
CS4
output
RAS4
output
WE
*
output
PH0
input
PH0
output
PH0
input
PH0
output
PH0
input
CS4
output
RAS4
output
WE
*
output
Note: * Not supported in the H8S/2456 Group.