Datasheet

Section 10 I/O Ports
Page 680 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
• PH2/CS6/IRQ6-B
The pin function is switched as shown below according to the combination of the operating
mode, bit CS6E in PFCR0, and bit PH2DDR.
Operating
mode
1, 2, 4 3, 7
EXPE ⎯ 0 1
CS6E 0 1 ⎯ 0 1
PH2DDR 0 1 0 1 0 1 0 1 0 1
PH2
input
PH2
output
PH2
input
CS6
output
PH2
input
PH2
output
PH2
input
PH2
output
PH2
input
CS6
output
Pin
function
IRQ6-B interrupt input
*
Note: * IRQ6-B input when the ITS6 bit in ITSR is 1.
• PH1/CS5/RAS5/SDRAMφ*
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit SDPSTP in
SCKCR of the clock pulse generator, bit CS5E in PFCR0 and bit PH1DDR.
SDPSTP 1 0
Operating
mode
1, 2, 4 3, 7 ⎯
EXPE ⎯ 0 1 ⎯
RMTS2 to
RMTS0
Area 5 is normal space Area 5 is DRAM
space
⎯ Area 5 is normal space Area 5 is DRAM
space
⎯
CS5E 0 1 0 1 ⎯ 0 1 0 1 ⎯
PH1DDR 0 1 0 1 0 1 ⎯ 0 1 0 1 0 1 0 1 ⎯ ⎯
Pin
function
PH1
input
PH1
output
PH1
input
CS5
output
PH1
input
PH1
output
RAS5
output
PH1
input
PH1
output
PH1
input
PH1
output
PH1
input
CS5
output
PH1
input
PH1
output
RAS5
output
SDRAMφ
output
*
Note: * Not supported in the H8S/2456 Group.