Datasheet

Section 10 I/O Ports
Page 676 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Bit Bit Name Initial Value R/W Description
0 PH0DDR 0 W Pin PH1 functions as the SDRAMφ
*
output pin
when the SDPSTP bit is 0 in the H8S/2456R
Group. In the H8S/2456 Group or when the
SDPSTP bit is 1 in the H8S/2456R Group, if bit
CS5E is set to 1 while area 5 is specified as
normal space, pin PH1 functions as the CS5
output pin when bit PH1DDR is set to 1, and
functions as an I/O port when the bit is cleared to
0. When bit CS5E is cleared to 0, pin PH1 is an
I/O port, and its function can be switched with bit
PH1DDR. When area 5 is specified as DRAM
space and bit CS5E is set to 1, pin PH1 functions
as the RAS5 output pin and as an I/O port when
the bit is cleared to 0.
Pin PH0 functions as the CS4 output pin when
area 4 is specified as normal space and bit
PH0DDR is set to 1. If bit PH0DDR is cleared to
0, pin PH0 functions as an I/O port. When bit
CS4E is cleared to 0, pin PH0 is an I/O port, and
its function can be switched with bit PH0DDR.
When area 4 is specified as DRAM space and bit
CS4E is set to 1, pin PH0 functions as the RAS4
output pin and as an I/O port when the bit is
cleared to 0. When areas 2 to 5 are specified as
continuous SDRAM space
*
, pin PH0 functions as
the WE output pin when bit CS4E is set to 1, and
as an I/O port when the bit is cleared to 0.
• Modes 3 and 7 (EXPE = 0)
Pins PH3, PH2, and PH0 are I/O ports, and their
functions can be switched with PHDDR.
Pin PH1 functions as the SDRAMφ output pin
when the SDPSTP bit is 0 in the H8S/2456R
Group. In the H8S/2456 Group or when the
SDPSTP bit is 1 in the H8S/2456R Group, pin
PH1 is an I/O port and its function can be
switched with PHDDR.
Note: * Not supported in the H8S/2456 Group.