Datasheet

Section 10 I/O Ports
Page 674 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
• PG2/CS2/ RAS2/RAS*
The pin function is switched as shown below according to the combination of the operating
mode, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS2E in PFCR0, and bit
PG2DDR.
Operating
mode
1, 2, 4 3, 7
EXPE ⎯ 0 1
CS2E 0 1 ⎯ 0 1
RMTS2 to
RMTS0
⎯ Area 2 is in
normal space
Area 2 is in
DRAM space
and areas 2 to 5
are in
synchronous
DRAM space
Areas 2 to 5 are
in
synchronous
DRAM* space
⎯ ⎯ Area 2 is in
normal space
Area 2 is in
DRAM space
and areas 2 to 5
are in
synchronous
DRAM space
Areas 2 to 5
are in
synchronous
DRAM space
PG2DDR 0 1 0 1 ⎯ ⎯ 0 1 0 1 0 1 ⎯ ⎯
Pin function PG2
input
PG2
output
PG2
input
CS2
output
RAS2
output
RAS*
output
PG2
input
PG2
output
PG2
input
PG2
output
PG2
input
CS2
output
RAS2
output
RAS*
output
Note: * Not supported in the H8S/2456 Group and H8S/2454 Group.
• PG1/CS1, PG0/CS0
The pin function is switched as shown below according to the combination of the operating
mode, bit CSnE in PFCR0, and bit PGnDDR.
Operating
mode
1, 2, 4 3, 7
EXPE ⎯ 0 1
CSnE 0 1 ⎯ 0 1
PGnDDR 0 1 0 1 0 1 0 1 0 1
Pin
function
PGn
input
PGn
output
PGn
input
CSn
output
PGn
input
PGn
output
PGn
input
PGn
output
PGn
input
CSn
output
[Legend]
n = 1 or 0