Datasheet

Section 10 I/O Ports
R01UH0309EJ0500 Rev. 5.00 Page 673 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
• Modes 3 and 7 (EXPE = 0)
BRLE ⎯
BREQOE
BREQOS
⎯
CS4E 0 1
PG4DDR 0 1 ⎯
Pin function PG4 input PG4 output CS4 output*
Notes: * Not supported in the H8S/2456 Group and H8S/2456R Group.
• PG3/CS3/RAS3/CAS
*
The pin function is switched as shown below according to the combination of the operating
mode, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS3E in PFCR0, and bit
PG3DDR.
Operating
mode
1, 2, 4 3, 7
EXPE ⎯ 0 1
CS3E 0 1 ⎯ 0 1
RMTS2 to
RMTS0
⎯ Area 3 is in
normal space
Area 3 is
in DRAM
space
Areas 2 to 5
are in
synchronous
DRAM* space
⎯ ⎯ Area 3 is in
normal space
Area 3 is
in DRAM
space
Areas 2 to 5
are in
synchronous
DRAM space
PG3DDR 0 1 0 1 ⎯ ⎯ 0 1 0 1 0 1 ⎯ ⎯
Pin function PG3
input
PG3
output
PG3
input
CS3
output
RAS3
output
CAS*
output
PG3
input
PG3
output
PG3
input
PG3
output
PG3
input
CS3
output
RAS3
output
CAS*
output
Note: * Not supported in the H8S/2456 Group and H8S/2454 Group.