Datasheet

Section 10 I/O Ports
Page 672 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
• PG5/BACK-A
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BACKS in PFCR4, and bit
PG5DDR.
Operating
mode
1, 2, 4 3, 7
EXPE ⎯ 0 1
BRLE
BACKS
BRLE = 0 or
BRLE = 1 and
BACKS = 1
BRLE = 1
and
BACKS = 0
⎯ BRLE = 0 or
BRLE = 1 and
BACKS = 1
BRLE = 1
and
BACKS = 0
PG5DDR 0 1 ⎯ 0 1 0 1 ⎯
Pin
function
PG5
input
PG5
output
BACK-A
output
PG5
input
PG5
output
PG5 input PG5
output
BACK-A
output
• PG4/BREQO-A/CS4*
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BREQOE, bit BREQOS in
PFCR4, bit SC4E in PFCR0, and bit PG4DDR.
• Modes 1, 2, and 4 Modes 3 and 7 (EXPE = 1)
BRLE 0 1
BREQOE
BREQOS
⎯ BREQOE = 0 or BREQOE =
1 and BREQOS = 1
BREQOR = 1 and
BREQOS = 0
CS4E 0 1 0 1 ⎯
PG4DDR 0 1 ⎯ 0 1 ⎯ ⎯
Pin function PG4
input
PG4
output
CS4
output*
PG4
input
PG4
output
CS4
output*
BREQO-A output