Datasheet

Section 10 I/O Ports
R01UH0309EJ0500 Rev. 5.00 Page 671 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
10.15.4 Port G Open Drain Control Register (PGODR)
PGODR specifies the output type of each port G pin.
Bit Bit Name Initial Value R/W Description
7 ⎯ 0 ⎯ Reserved
This bit is always read as 0. Only the initial value
should be written to this bit.
6 PG6ODR 0 R/W
5 PG5ODR 0 R/W
4 PG4ODR 0 R/W
3 PG3ODR 0 R/W
2 PG2ODR 0 R/W
1 PG1ODR 0 R/W
0 PG0ODR 0 R/W
When not specified for BACK-A, BREQO-A, CS0,
CS1, CS2, CS3, CS4*
2
, RAS2, RAS3, RAS*
1
, or
CAS*
1
output, setting a PGODR bit to 1 makes the
corresponding pin an NMOS open-drain output pin,
while clearing a PGODR bit to 0 makes the
corresponding pin a CMOS output pin.
Notes: 1. Not supported in the H8S/2456 and 2454 Groups.
2. Not supported in the H8S/2456 and 2456R Groups.
10.15.5 Pin Functions
Port G pins also function as the pins for bus control signal I/Os. The correspondence between the
register specification and the pin functions is shown below.
• PG6/BREQ-A
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BREQS in PFCR4, and bit
PG6DDR.
Operating mode 1, 2, 4 3, 7
EXPE ⎯ 0 1
BRLE
BREQS
BRLE = 0 or
BRLE = 1 and
BREQS = 1
BRLE = 1
and
BREQS = 0
⎯ BRLE = 0 or
BRLE = 1 and
BREQS = 1
BRLE = 1
and
BREQS = 0
PG6DDR 0 1 ⎯ 0 1 0 1 ⎯
Pin function PG6
input
PG6
output
BREQ-A
input
PG6
input
PG6
output
PG6
input
PG6
output
BREQ-A input