Datasheet

Section 10 I/O Ports
Page 664 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
SSU settings (1) (2) (1) (3) (1) (2) (1) (3)
SSUMS 0 1
MSS 0 1 0 1
SCKS 0 1 0 1 0 1 0 1
Pin state ⎯ SSCK
input
⎯ SSCK
output
⎯ SSCK
input
⎯ SSCK
output
[Legend]
⎯: Not used as the SSU pin (can be used as an I/O port).
Note: See tables 20.4 to 20.6.
• PF0/WAIT-A/ADTRG0-B/SCS0-C (H8S/2456 Group and H8S/2456R Group)
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit WAITE in BCR of the bus controller, bits MSS, CSS1, and CSS0 in
SSCRH and bit SSUMS in SSCRL of SSU, bits TRGS1, TRGS0, and EXTRGS in ADCR_0
of ADC, bits ADTRG0S and WAITS in PFCR4, bits SCS0S1 and SCS0S0 in PFCR5, and bit
PF0DDR.
• Modes 1, 2, and 4 Modes 3 and 7 (EXPE = 1)
WAITE 0
WAITS ⎯
SSU settings (1) in table below (2) in table below (4) in table below (3) in table below
PF0DDR 0 1 0*
5
0*
5
⎯
PF0 input PF0 output SCS0-C input*
2
*
6
SCS0-C I/O*
4
*
6
SCS0-C output*
3
*
6
Pin function
ADTRG0-B input*
1
WAITE 1
WAITS 0 1
SSU settings ⎯ (1) in table
below
(2) in table
below
(4) in table
below
(3) in table
below
⎯
PF0DDR ⎯ 0 0*
5
0 0 1
WAIT-A input PF0 input SCS0-C
input*
2
*
6
Setting
prohibited
Setting
prohibited
Setting
prohibited
Pin function
ADTRG0-B input*
1