Datasheet

Section 10 I/O Ports
Page 654 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Bit Bit Name
Initial
Value R/W Description
[H8S/2454 Group]
Pins PF2 and PF1 function as CS output pins when the
CS output enable bits (CS6E and CS5E) are set to 1,
and as input ports when the bits are cleared to 0. When
the CS output enable bits (CS6E and CS5E) are cleared
to 0 and pins PF2 and PF1 are general I/O ports, the
function can be switched with PFDDR.
The PF0 pin functions as a bus control input pin (WAIT)
when the appropriate bus controller settings are made.
Otherwise, PF0 is an I/O port and the function can be
switched with PF0DDR.
• Modes 3 and 7 (EXPE = 0)
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an input port
when the bit is cleared to 0.
Pins PF6 to PF0 are I/O ports, and their functions can be
switched with PFDDR.
Note: * PF7DDR is initialized to 1 in modes 1, 2, and 4, and to 0 in modes 3 and 7.