Datasheet

Section 10 I/O Ports
Page 648 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
10.13.2 Port E Data Register (PEDR)
PEDR stores output data for the port E pins.
Bit Bit Name Initial Value R/W Description
7 PE7DR 0 R/W
6 PE6DR 0 R/W
5 PE5DR 0 R/W
4 PE4DR 0 R/W
3 PE3DR 0 R/W
2 PE2DR 0 R/W
1 PE1DR 0 R/W
0 PE0DR 0 R/W
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.
10.13.3 Port E Register (PORTE)
PORTE shows the pin states of port E. PORTE cannot be modified.
Bit Bit Name Initial Value R/W Description
7 PE7 ⎯* R
6 PE6 ⎯* R
5 PE5 ⎯* R
4 PE4 ⎯* R
3 PE3 ⎯* R
2 PE2 ⎯* R
1 PE1 ⎯* R
0 PE0 ⎯* R
If this register is read while a PEDDR bit is set to 1,
the corresponding PEDR value is read. If this
register is read while a PEDDR bit is cleared to 0,
the corresponding pin state is read.
Note: * Determined by the states of pins PE7 to PE0.