Datasheet

Section 10 I/O Ports
Page 640 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
• PC0/A0/TIOCA9
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOA3 to
IOA0 in TIORH_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC0DDR.
Operating
mode
1, 2 4 3, 7 (EXPE = 1) 3, 7 (EXPE = 0)
TPU channel
9 settings
⎯ ⎯ (1) in table
below
(2) in table below
PC0DDR ⎯ 0 1 ⎯ 0 1
PC0 input PC0 output Pin function A0 output PC0 input A0 output TIOCA9
output
TIOCA9 input*
1
TPU channel 9
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOA3 to IOA0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00 Other than B'xx00
CCLR2 to
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'001
B'001
Output function ⎯ Output
compare
output
⎯ PWM*
2
mode
1 output
PWM mode
2 output
⎯
[Legend]
x: Don't care
Notes: 1. TIOCA9 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx.
2. TIOCB9 output disabled.