Datasheet

Section 1 Overview
R01UH0309EJ0500 Rev. 5.00 Page 37 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Pin No.
H8S/2456, H8S/2456R
H8S/2454
Type Symbol PLQP0144KA-A
PTLG0145JB-A
PLQP0120LA-A,
PLQP0120KA-A I/O Function
Bus
control
WAIT-A
WAIT-B
84
56
J11
N7
69
47
Input Requests insertion of a wait state in
the bus cycles when accessing an
external 3-state address space.
OE-A
OE-B
38
137
M2
A5
69
113
Output Output enable signal when
accessing the DRAM space.
CKE-A*
1
CKE-B*
1
38
137
M2
A5
⎯
⎯
Output Clock enable signal when the
synchronous DRAM interface is set.
Interrupts NMI 40 N1 32 Input Nonmaskable interrupt request pin.
This pin should be fixed high when
not used.
IRQ15-A
to
IRQ8-A*
2
86, 85,
106 to 104,
83 to 81
H10, H12, C13, D12,
D10, J10, K13, J12
⎯
IRQ7-A to
IRQ0-A
31 to 28,
136 to 133
J3, K2, J1, K4, D4,
C6, B5, A6
29 to 26,
112 to 109
IRQ15-B
to
IRQ13-B*
2
IRQ8-B*
2
58 to 56
51
K7, L8, N7, L6 ⎯
IRQ7-B to
IRQ0-B
38, 37,
61 to 59,
34, 33, 3
M2, N2, M8, N8, K8,
K3, L2, C2
102 to 95
These pins request a maskable
interrupt.
The input pins of IRQn-A and IRQn-
B are selected by the IRQ pin select
register (ITSR) of the interrupt
controller.
(n = 0 to 15, m=0 to 8, 13 to 15 for
the H8S/2456R Group and
H8S/2456)
(n = 0 to 7 for the H8S/2454 Group)
DREQ1
DREQ0
82
81
K13, J12 35
34
Input These signals request DMAC
activation.
DMA
controller
(DMAC)
TEND1
TEND0
104
83
D10
J10
37
36
Output These signals indicate the end of
DMAC data transfer.
DACK1
DACK0
106
105
C13
D12
39
38
Output DMAC single address transfer
acknowledge signals.
EDREQ3
EDREQ2
33
3
L2
C2
⎯ Input These signals request EXDMAC
activation.
EXDMA
controller
(EXDMAC)
*
2
ETEND3
ETEND2
59
34
K8
K3
⎯ Output These signals indicate the end of
EXDMAC data transfer.
EDACK3
EDACK2
61
60
M8
N8
⎯ Output EXDMAC single address transfer
acknowledge signals.