Datasheet

Section 1 Overview
Page 36 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Pin No.
H8S/2456, H8S/2456R
H8S/2454
Type Symbol PLQP0144KA-A
PTLG0145JB-A
PLQP0120LA-A,
PLQP0120KA-A I/O Function
Bus
control
BREQO-A
BREQO-B
130
133
B6
A6
106
109
Output External bus request signal when
the internal bus master accesses an
external space in the external bus
release state.
BACK-A
BACK-B
131
135
C7
C6
107
111
Output Indicates the bus is released to the
external bus master.
UCAS 85 H12 70 Output Upper column address strobe signal
for accessing the 16-bit DRAM
space. Also functions as the column
address strobe signal for accessing
the 8-bit DRAM space.
LCAS 86 H10 71 Output Lower column address strobe signal
for accessing the 16-bit DRAM
space.
DQMU
*
1
85 H12 ⎯ Output Upper data mask enable signal for
accessing the 16-bit continuous
synchronous DRAM space. Also
functions as the data mask enable
signal for accessing the 8-bit
continuous synchronous DRAM
space.
DQML
*
1
86 H10 ⎯ Output Lower-data mask enable signal for
accessing the 16-bit continuous
synchronous DRAM interface
space.
RAS2
RAS3
RAS4
*
2
RAS5
*
2
109
110
35
36
A12
A13
L1
M1
91
92
⎯
⎯
Output Row address strobe signal for the
DRAM when the DRAM interface is
set. Row address strobe signal
when areas 2 to 5 are set as the
continuous DRAM space.
RAS
*
1
109 A12 ⎯ Output Row address strobe signal for the
synchronous DRAM when the
synchronous DRAM interface is set.
CAS
*
1
110 A13 ⎯ Output Column address strobe signal for
the synchronous DRAM when the
synchronous DRAM interface is set.
WE
*
1
35 L1 ⎯ Output Write enable signal for the
synchronous DRAM when the
synchronous DRAM interface is set.