Datasheet

Section 10 I/O Ports
Page 626 of 1408 R01UH0309EJ0500 Rev. 5.00
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
• PB2/A10/TIOCC6/TCLKE
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOC3 to
IOC0 in TIORL_6, and bits CCLR2 to CCLR0 in TCR_6), bits TPSC2 to TPSC0 in TCR_6 to
TCR_11, and bit PB2DDR.
Operating
mode
1, 2 4 3, 7 (EXPE = 1) 3, 7 (EXPE = 0)
TPU channel
6 settings
⎯ ⎯ (1) in table
below
(2) in table below
PB2DDR ⎯ 0 1 ⎯ 0 1
PB2 input PB2 output TIOCC6
output
TIOCC6 input*
1
Pin function A10 output PB2 input A10 output
TCLKE input*
2
TPU channel 6
settings
(2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOC3 to IOC0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
B'xx00 Other than B'xx00
CCLR2 to
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'101
B'101
Output function ⎯ Output
compare
output
⎯ PWM*
3
mode
1 output
PWM mode
2 output
⎯
[Legend]
x: Don't care
Notes: 1. TIOCC6 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
2. TCLKE input when the setting for any of TCR_6 to TCR_11 is TPSC2 to TPSC0 =
B'100. TCLKE input when phase counting mode is set for channels 7 and 11.
3. TIOCD6 output disabled. Output disabled and settings (2) effective when BFA = 1 or
BFB = 1 in TMDR_6.