Datasheet

Section 10 I/O Ports
R01UH0309EJ0500 Rev. 5.00 Page 623 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
• PB5/A13/TIOCB7/TCLKG
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, TPU channel 7 settings (by bits MD3 to MD0 in TMDR_7, bits IOB3 to
IOB0 in TIOR_7, and bits CCLR1 and CCLR0 in TCR_7), bits TPSC2 to TPSC0 in TCR_6,
TCR_8, TCR_10, and TCR_11, and bit PB5DDR.
Operating
mode
1, 2 4 3, 7 (EXPE = 1) 3, 7 (EXPE = 0)
TPU channel
7 settings
⎯ ⎯ (1) in table
below
(2) in table below
PB5DDR ⎯ 0 1 ⎯ 0 1
PB5 input PB5 output TIOCB7
output
TIOCB7 input*
1
Pin function A13 output PB5 input A13 output
TCLKG input*
2
TPU channel 7
settings
(2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB3 to IOB0 B'0000,
B'0100,
B'1xxx
B'0001 to
B'0011,
B'0101 to
B'0111
⎯ B'xx00 Other than B'xx00
CCLR1,
CCLR0
⎯ ⎯ ⎯ ⎯ Other than
B'10
B'10
Output function ⎯ Output
compare
output
⎯ ⎯ PWM mode
2 output
⎯
[Legend]
x: Don't care
Notes: 1. TIOCB7 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.
2. TCLKG input when the setting for either TCR_6 or TCR_8 is TPSC2 to TPSC0 = B'111,
or when the setting for either TCR_10 or TCR_11 is TPSC2 to TPSC0 = B'101. TCLKG
input when phase counting mode is set for channels 8 and 10.