Datasheet

Section 1 Overview
R01UH0309EJ0500 Rev. 5.00 Page 35 of 1408
Sep 24, 2012
H8S/2456, H8S/2456R, H8S/2454 Group
Pin No.
H8S/2456, H8S/2456R
H8S/2454
Type Symbol PLQP0144KA-A
PTLG0145JB-A
PLQP0120LA-A,
PLQP0120KA-A I/O Function
Address
bus
A23 to A0 31 to 26,
24 to 19,
17 to 11,
9 to 5
J3, K2, J1, K4,
H3, J2, J4, G3,
H2, G1, H4, G4,
F1, G2, F3, E4,
E1, F2, E3, D1,
D3, D2, C3, C1
29 to 23,
21 to 18,
16 to 9,
7 to 3
Output These pins output an address.
Data bus D15 to D0 80 to 73,
71,
69 to 63
K11, K12, L13,
L11, M12, L12,
N13, M13, N11,
M11, N10, L9,
M10, N9, K10, L8
68 to 61,
59,
57 to 51
Input/
output
These pins constitute a bidirectional
data bus. When an address/data
multiplexed I/O space is accessed,
an address is also output.
Address/
data
multiplexed
bus
AD15 to
AD0
80 to 73,
71,
69 to 63
K11, K12, L13,
L11, M12, L12,
N13, M13, N11,
M10, N10, K10,
L10, M9, N9, K9
68 to 61,
59,
57 to 51
Input/
output
These pins output an address, and
input or output data.
Bus
control
CS7 to
CS0
38 to 35,
110 to 107
M2, N2, M1, L1,
A13, A12, B13,
C12
29, 71, 70, 106,
92 to 89
Output Signals that select division areas 7
to 0 in the external address space
AS 90 G10 75 Output When this pin is low, it indicates that
address output on the address bus
is valid.
AH 90 G10 75 Output Signal for holding the address when
an address/data multiplexed I/O
space is being accessed.
RD 89 G12 74 Output When this pin is low, it indicates that
the external address space is being
read.
HWR 88 H11 73 Output Strobe signal indicating that an
external address space is to be
written to, and the upper half (D15
to D8) of the data bus is enabled.
Also functions as the write enable
signal for accessing the DRAM
space.
LWR 87 J13 72 Output Strobe signal indicating that an
external address space is to be
written to, and the lower half (D7 to
D0) of the data bus is enabled.
BREQ-A
BREQ-B
132
134
D5
B5
108
110
Input The external bus master requests
the bus to this LSI.